Neural network memory
An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.
1. An apparatus, comprising:
a memory array comprising:
a first portion comprising a first plurality of variable resistance memory cells; and
a second portion comprising a second plurality of variable resistance memory cells that have been degraded through forced write cycling; and
a memory controller coupled to the first portion and the second portion, wherein the memory controller is configured to:
operate the first portion for short-term memory operations; and
operate the second portion for long-term memory operations; and
perform the forced write cycling on the second plurality of variable resistance memory cells prior to operating the second portion.
2. The apparatus of claim 1 , wherein the memory controller is configured to operate the first portion for short-term memory operations by applying a RESET read disturb pulse to change a conductance of any of the first plurality of variable resistance memory cells to which the RESET read disturb is applied, wherein the conductance represents a synaptic weight or a portion of a synaptic weight.
3. The apparatus of claim 1 , wherein the memory controller is configured to operate the first portion for short-term memory operations by performing a short SET pulse to change a conductance of any of the first plurality of variable resistance memory cells to which the short SET pulse is applied;
wherein the conductance represents a synaptic weight or a portion of a synaptic weight.
4. The apparatus of claim 1 , wherein the memory controller is configured to operate the first portion for short-term memory operations by applying a pulse to increase a conductance of any of the first plurality of memory cells while in a RESET state and without transitioning to a SET state;
wherein increasing the conductance represents an increase to a short-term synaptic weight.
5. The apparatus of claim 4 , wherein the memory controller is configured to operate the first portion for short-term memory operations by resetting the conductance of any of the first plurality of memory cells.
6. The apparatus of claim 5 , wherein the memory controller is configured to operate the second portion for long-term memory operations by applying a pulse to increase a conductance of any of the second plurality of variable resistance memory cells while in a RESET state having a greater conductance than the RESET state of the first plurality of variable resistance memory cells;
wherein increasing the conductance represents an increase to a long-term synaptic weight.
7. The apparatus of claim 1 , wherein the memory controller configured to perform the forced write cycling comprises the memory controller configured to perform at least 10,000 forced write cycles.
8. The apparatus of claim 1 , wherein the memory controller configured to perform the forced write cycling comprises the memory controller configured to cause the second plurality of variable resistance memory cells to be in a degradation condition greater than a degradation condition of the first plurality of variable resistance memory cells.
9. The apparatus of claim 1 , wherein the memory controller configured to perform the forced write cycling comprises the memory controller configured to irreversibly increase a conductance associated with each of the second plurality of variable resistance memory cells.
10. The apparatus of claim 1 , wherein the memory controller configured to perform the number of short-term memory operations comprises the memory controller configured to perform fewer than 1000 short-term memory operations on any of the first plurality of variable resistance memory cells.
11. An apparatus, comprising:
a memory array comprising:
a first portion comprising a first plurality of variable resistance memory cells; and
a second portion comprising a second plurality of variable resistance memory cells that have been degraded; and
a memory controller coupled to the memory array, wherein the memory controller is configured to:
operate the first portion for short-term memory operations;
operate the second portion for long-term memory operations; and
reclassify a particular one of the first plurality of variable resistance memory cells as one of the second plurality of variable resistance memory cells in response to an operating criterion being met.
12. The apparatus of claim 11 , wherein the operating criterion comprises more than a threshold number of short-term memory operations being performed on the particular one of the first plurality of variable resistance memory cells.
13. The apparatus of claim 11 , wherein the operating criterion comprises a conductance of the particular one of the first plurality of variable resistance memory cells being greater than a threshold value while in a RESET state.
14. The apparatus of claim 11 , wherein the memory controller is configured to perform forced write cycling on the particular one of the first plurality of variable resistance memory cells prior to operating particular one of the first plurality of variable resistance memory cells for long-term memory operations.
15. The apparatus of claim 11 , wherein the memory controller configured to operate the first portion for short-term memory operations comprises the memory controller configured to change a conductance of each of a subset of the first plurality of variable resistance memory cells, the conductance corresponding to data of a learning algorithm; and
wherein the memory controller is configured to move the data to a subset of the second plurality of memory cells in response to the learning algorithm indicating that long-term learning has occurred.
16. A method, comprising:
performing a first plurality of neural network operations on a plurality of short-term memory cells of a memory array;
performing a second plurality of neural network operations on a plurality of long-term memory cells of the memory array, and
transferring data stored in at least one of the plurality of short-term memory cells to be stored in at least one of the plurality of long-term memory cells;
wherein the data represents a synaptic weight with respect to the first plurality of neural network operations; and
wherein transferring the data comprises transferring the data in response to the first plurality of neural network operations indicating that long-term learning has occurred.
17. The method of claim 16 , wherein performing the first plurality of neural network operations comprises changing data stored in the first plurality of short-term memory cells corresponding to an increase in the synaptic weight with respect to the first plurality of neural network operations.
18. The method of claim 16 , wherein transferring the data comprises transferring in response to the synaptic weight being above a threshold synaptic weight.
19. A method, comprising:
operating a first portion of an array of variable resistance memory cells as short-term memory cells for neural network operations; and
operating a second portion of the array as long-term memory for the neural network operations;
wherein operating the first portion of the array comprises increasing a conductance of a first one of the variable resistance memory cells between a RESET state and a SET state to represent an increased synaptic weight for short-term memory with respect to the neural network operations;
wherein operating the second portion of the array comprises increasing a conductance of a second one of the plurality of variable resistance memory cells between a degraded RESET state and a degraded SET state to represent an increased synaptic weight for long-term memory with respect to the neural network operations;
wherein the degraded RESET state has a greater conductance than the RESET state; and
wherein the degraded SET state has a greater conductance than the SET state.
20. An apparatus, comprising:
a memory array comprising:
a first portion comprising a first plurality of variable resistance memory cells; and
a second portion comprising a second plurality of variable resistance memory cells that have been degraded through forced write cycling; and
a memory controller coupled to the first portion and the second portion, wherein the memory controller is configured to:
operate the first portion for short-term memory operations by applying a pulse to increase a conductance of any of the first plurality of memory cells while in a RESET state and without transitioning to a SET state;
wherein increasing the conductance represents an increase to a short-term synaptic weight; and
operate the second portion for long-term memory operations;
wherein increasing the conductance represents an increase to a short-term synaptic weight.