Solar cell and method of manufacturing the same
Disclosed is a solar cell including a semiconductor substrate, and a dopant layer disposed over one surface of the semiconductor substrate and having a crystalline structure different from that of the semiconductor substrate, the dopant layer including a dopant. The dopant layer includes a plurality of semiconductor layers stacked one above another in a thickness direction thereof, and an interface layer interposed therebetween. The interface layer is an oxide layer having a higher concentration of oxygen than that in each of the plurality of semiconductor layers.
1. A method for manufacturing a solar cell, the method comprising:
forming a tunneling layer formed of silicon oxide on one surface of a silicon substrate; and
forming a first conductive area including a first dopant on the tunneling layer,
wherein the forming of the first conductive area comprises:
forming a plurality of polycrystalline silicon layers including an undoped polycrystalline silicon layer and a doped polycrystalline silicon layer including the first dopant; and
heat-treating the plurality of polycrystalline silicon layers to form the first conductive area,
wherein the forming of the pluralit of polycrystalline silicon layers comprises:
forming a first undoped polycrystalline silicon layer on the silicon substrate; and
forming the doped polycrystalline silicon layer including the first dopant on the first undoped polycrystalline silicon layer, and
wherein a thickness of the doped polycrystalline silicon layer is smaller than a thickness of the first undoped polycrystalline silicon layer.
2. The method according to claim 1 , wherein the forming of the plurality of polycrystalline silicon layers further comprises:
forming a second undoped polycrystalline silicon layer on the doped polycrystalline silicon layer after the forming of the doped polycrystalline silicon layer.
3. The method according to claim 2 , wherein a thickness of the second undoped polycrystalline silicon layer is the same or smaller than the thickness of the doped polycrystalline silicon layer.
4. The method according to claim 2 , wherein a total thickness of the first and second undoped polycrystalline silicon layers is greater than the thickness of the doped polycrystalline silicon layer.
5. The method according to claim 2 , wherein, in the heat-treating, of the plurality of polycrystalline silicon layers, the first dopant included in the doped polycrystalline silicon layer is diffused into the first undoped polycrystalline silicon layer and the second undoped polycrystalline silicon layer to form the first conductive area.
6. The method according to claim 1 , wherein the plurality of polycrystalline silicon layers are formed by low pressure chemical vapor deposition (LPCVD).
7. The method according to claim 1 , wherein a temperature of the forming of the plurality of polycrystalline silicon layers is higher than a temperature of the heat-treating of the plurality of polycrystalline silicon layers.
8. The method according to claim 1 , wherein a temperature of the forming of the plurality of polycrystalline silicon layers is 600° C. or more.
9. The method according to claim 1 , wherein a temperature of the heat-treating of the plurality of polycrystalline silicon layers is 900° C. or more.
10. The method according to claim 1 , wherein the plurality of polycrystalline silicon layers are successively formed in the same equipment.
11. The method according to claim 10 , wherein the plurality of polycrystalline silicon layers are successively formed by changing supply gases in the same equipment.
12. The method according to claim 1 , further comprising:
forming a second conductive area at another surface of the silicon substrate.
13. The method according to claim 12 , wherein the forming of the first conductive area and the forming of the second conductive area are simultaneously performed by the same heat-treatment.
14. The method according to claim 12 , wherein the second conductive area has a conductive type opposite to a conductive type of the first conductive area or the silicon substrate.
15. The method according to claim 14 , wherein the second conductive area is formed by diffusing a second dopant to the another surface of the silicon substrate.
16. The method according to claim 1 , wherein the one surface of the silicon substrate is a back surface of the silicon substrate.
17. The method according to claim 16 , further comprising:
texturing the one surface of the silicon substrate.
18. The method according to claim 1 , further comprising, after the forming of the first conductive area:
forming a first passivation film on the first conductive area;
applying a paste for forming a first electrode on the first passivation film; and
forming a first electrode connected to first conductive area through penetrating the first passivation film by firing the paste for forming the first electrode.
19. The method according to claim 1 , further comprising, after the forming of the first conductive area:
forming a first passivation film on the first conductive area;
forming an opening at the first passivation film;
applying a paste for forming a first electrode through the opening on the first conductive area; and
forming a first electrode connected to first conductive area.
20. The method according to claim 19 , wherein the opening is formed by using laser ablation, etching solution, or etching paste.
21. The method according to claim 1 , wherein the silicon substrate and the first conductive area have different crystalline structures.
22. The method according to claim 1 , where the forming of the plurality of polycrystalline silicon layers further comprises forming an interface layer between the forming of the first undoped polycrystalline silicon layer and forming of the doped polycrystalline silicon layer.
23. The method according to claim 22 , wherein the interface layer is an oxide layer.