IP Library Granted Patent US 10,542,455
Granted Patent B2
US 10,542,455 · App. 16/505,083 · Granted Jan 21, 2020

Data indication method and apparatus and communication system

Inventors: Yulong Shi (Beijing, CN); Pengyu Ji (Beijing, CN); Hua Zhou (Beijing, CN)
Assignee: Fujitsu Limited
H04W28/0278H04W28/0252H04W28/06H04W80/02
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Quick Facts
Patent No.
US 10,542,455
App. No.
16/505,083
Granted
Jan 21, 2020
Kind
B2
Abstract

A data indication method includes: transmitting a buffer status report to a network side, the buffer status report containing at least one piece of buffer size information, the buffer size information indicating a buffer size to which a logical channel or a logical channel group corresponds; or transmitting a buffer status report of a variable length to a network side; wherein, the buffer status report of a variable length contains buffer size information on a logical channel group with a buffer size being greater than zero when the buffer status report is triggered or before logical channel data are multiplexed, or contains buffer size information on a logical channel group with a buffer size being greater than zero before logical channel data are multiplexed and being equal to zero after the logical channel data are multiplexed.

Claims (220)

1. A data indication apparatus, comprising:

a memory that stores a plurality of instructions; and

a processor coupled to the memory and configured to execute the instructions to:

transmit a buffer status report to a network side, the buffer status report comprising a 3 bit logical channel group (LCG) ID field and a 5 bit buffer size field, wherein the buffer size field indicates a buffer size corresponding to a LCG,

wherein a value range of the buffer size field is defined in the buffer status report table

Index

Buffer Size (BS) value [bytes]

0

BS = 0

1

 0 < BS <= 10

2

10 < BS <= 14

3

14 < BS <= 20

4

20 < BS <= 28

5

28 < BS <= 38

6

38 < BS <= 53

7

53 < BS <= 74

8

 74 < BS <= 102

9

102 < BS <= 142

10

142 < BS <= 198

11

198 < BS <= 276

12

276 < BS <= 384

13

384 < BS <= 535

14

535 < BS <= 745

15

 745 < BS <= 1038

16

1038 < BS <= 1446

17

1446 < BS <= 2014

18

2014 < BS <= 2806

19

2806 < BS <= 3909

20

3909 < BS <= 5446

21

5446 < BS <= 7587

22

 7587 < BS <= 10570

23

10570 < BS <= 14726

24

14726 < BS <= 20516

25

20516 < BS <= 28581

26

28581 < BS <= 39818

27

39818 < BS <= 55474

28

55474 < BS <= 77284

29

 77284 < BS <= 107669

30

107669 < BS <=150000

31

BS > 150000.

2. The data indication apparatus according to claim 1 , wherein the 5 bit buffer size field corresponds with an index value in the buffer status report table.

3. The data indication apparatus according to claim 2 , wherein index values in the buffer status report table vary from 0 to 31.

4. A data indication apparatus, comprising:

a memory that stores a plurality of instructions; and

a processor coupled to the memory and configured to execute the instructions to:

receive a buffer status report transmitted by a UE, the buffer status report comprising a 3 bit logical channel group (LCG) ID field and a 5 bit buffer size field, wherein the buffer size field indicates a buffer size corresponding to a LCG,

wherein a value range of the buffer size field is defined in the buffer status report table

Buffer Size (BS) value

Index

[bytes]

0

BS = 0

1

 0 < BS <= 10

2

10 < BS <= 14

3

14 < BS <= 20

4

20 < BS <= 28

5

28 < BS <= 38

6

38 < BS <= 53

7

53 < BS <= 74

8

 74 < BS <= 102

9

102 < BS <= 142

10

142 < BS <= 198

11

198 < BS <= 276

12

276 < BS <= 384

13

384 < BS <= 535

14

535 < BS <= 745

15

 745 < BS <= 1038

16

1038 < BS <= 1446

17

1446 < BS <= 2014

18

2014 < BS <= 2806

19

2806 < BS <= 3909

20

3909 < BS <= 5446

21

5446 < BS <= 7587

22

 7587 < BS <= 10570

23

10570 < BS <= 14726

24

14726 < BS <= 20516

25

20516 < BS <= 28581

26

28581 < BS <= 39818

27

39818 < BS <= 55474

28

55474 < BS <= 77284

29

 77284 < BS <= 107669

30

107669 < BS <= 150000

31

BS > 150000.

5. The data indication apparatus according to claim 4 , wherein the 5 bit buffer size a field corresponds with an index value in the buffer status report table.

6. The data indication apparatus according to claim 5 , wherein index values in the buffer status report table vary from 0 to 31.

7. A communication system, comprising a UE and a network device wherein

the UE comprising a memory and a processor coupled to the memory, and the UE is configured to transmit a buffer status report to the network device, the buffer status report comprising a 3 bit logical channel group (LCG) ID field and a 5 bit buffer size field, wherein the buffer size field indicates a buffer size corresponding to a LCG, and

the network device is configured to receive the buffer status report,

wherein a value range of the buffer size field is defined in the buffer status report table

Index

Buffer Size (BS) value [bytes]

0

BS = 0

1

 0 < BS <= 10

2

10 < BS <= 14

3

14 < BS <= 20

4

20 < BS <= 28

5

28 < BS <= 38

6

38 < BS <= 53

7

53 < BS <= 74

8

 74 < BS <= 102

9

102 < BS <= 142

10

142 < BS <= 198

11

198 < BS <= 276

12

276 < BS <= 384

13

384 < BS <= 535

14

535 < BS <= 745

15

 745 < BS <= 1038

16

1038 < BS <= 1446

17

1446 < BS <= 2014

18

2014 < BS <= 2806

19

2806 < BS <= 3909

20

3909 < BS <= 5446

21

5446 < BS <= 7587

22

 7587 < BS <= 10570

23

10570 < BS <= 14726

24

14726 < BS <= 20516

25

20516 < BS <= 28581

26

28581 < BS <= 39818

27

39818 < BS <= 55474

28

55474 < BS <= 77284

29

 77284 < BS <= 107669

30

107669 < BS <= 150000

31

BS > 150000.

8. The communication system according to claim 7 , wherein the network device determines the buffer size to which LCG corresponds according to the buffer size field, and allocates resources for the UE according to the buffer size.

9. The communication system according to claim 7 , wherein the 5 bit buffer size field corresponds with an index value in the buffer status report table.

10. The communication system according to claim 9 , wherein index values in the buffer status report table vary from 0 to 31.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2025
From: FUJITSU LIMITED
To: 1FINITY INC.
Reel/Frame 072436/0098 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2019
From: SHI, YULONG; JI, PENGYU; ZHOU, HUA
To: FUJITSU LIMITED
Reel/Frame 049701/0860 →
Priority Claims (1)
WO PCT/CN2017/088471 · Jun 15, 2017 · international
Continuity (2)
Continuation PCTCN2017103702 · Sep 27, 2017
Related Publication 20190335357A1 · Oct 31, 2019