Detecting and correcting cache memory leaks
Embodiments of the present disclosure relate to an apparatus comprising a memory and at least one processor. The at least one processor is configured to monitor one or more processing threads of a storage device. Each of the one or more processing threads includes two or more cache states. The at least one processor also updates one or more data structures to indicate a subject cache state of each of the one or more processing threads and detect an event that disrupts at least one of the one or more processing threads. Further, the processor determines a cache state of the at least one of the one or more processing threads contemporaneous to the disruption event using the one or more data structures and performs a recovery process for the disrupted at least one of the one or more processing threads.
1. An apparatus comprising a memory and at least one processor configured to:
monitor one or more processing threads of a storage device, wherein each of the one or more processing threads includes at least one processing step that adjusts a state of at least one cache slot;
update one or more data structures to indicate a processing status of each of the one or more processing threads;
update the one or more data structures to indicate the state of the at least one cache slot in response to an execution of the at least one processing step;
detect an event that disrupts at least one of the one or more processing threads;
in response to detecting the event, identify the states of the one or more processing threads and the at least one cache slot using the at least one or more data structures; and
perform a recovery process for the at least one cache slot by selecting a recovery node including instructions for recovering the cache slot based in the identified states.
2. The apparatus of claim 1 further configured to generate a state machine unique to each of the one or more processing threads.
3. The apparatus of claim 2 , wherein each state machine is configured to update the one or more data structures to indicate the subject cache state of each of the one or more processing threads.
4. The apparatus of claim 1 , wherein each of the one or more data structures corresponds to a respective one of the one or more processing threads.
5. The apparatus of claim 1 further configured to generate a recovery state machine for each of the one or more processing threads, wherein each state of the recovery state machine indicates a recovery action for a respective one of the one or more processing threads.
6. The apparatus of claim 5 further configured to provide the recovery state machine with the cache state contemporaneous to the disruption event.
7. The apparatus of claim 6 further configured to configure the recovery state machine to perform the recovery action corresponding to the cache state of the one or more processing threads contemporaneous to the disruption event.
8. The apparatus of claim 1 further configured to scale a size of the one or more data structures based on a number of the one or more processing threads.
9. The apparatus of claim 1 wherein a disruption event includes one or more of the following: unexpected power-loss, software exception, and hardware failure or exception.
10. A method comprising:
monitoring one or more processing threads of a storage device, wherein each of the one or more processing threads includes at least one processing step that adjusts a state of at least one cache slot;
updating one or more data structures to indicate a processing status of each of the one or more processing threads;
updating the one or more data structures to indicate the state of the at least one cache slot in response to an execution of the at least one processing step;
detecting an event that disrupts at least one of the one or more processing threads;
in response to detecting the event, identifying the states of the one or more processing threads and the at least one cache slot using the at least one or more data structures; and
performing a recovery process for the at least one cache slot by selecting a recovery node including instructions for recovering the cache slot based in the identified states.
11. The method of claim 10 further comprising generating a state machine unique to each of the one or more processing threads.
12. The method of claim 11 further comprising updating the one or more data structures to indicate the subject cache state of each of the one or more processing threads using each generated state machine.
13. The method of claim 10 , wherein each of the one or more data structures corresponds to a respective one of the one or more processing threads.
14. The method of claim 10 further comprising generating a recovery state machine for each of the one or more processing threads, wherein each state of the recovery state machine indicates a recovery action for a respective one of the one or more processing threads.
15. The method of claim 14 further comprising providing the recovery state machine with the cache state contemporaneous to the disruption event.
16. The method of claim 15 further comprising performing the recovery action corresponding to the cache state of the one or more processing threads contemporaneous to the disruption event using the recovery state machine.
17. The method of claim 10 further comprising scaling a size of the one or more data structures based on a number of the one or more processing threads.
18. The method of claim 10 wherein a disruption event includes one or more of the following: unexpected power-loss, software exception, and hardware failure or exception.