Architectural data mover for RAID XOR acceleration in a virtualized storage appliance
Systems and methods for I/O acceleration in a virtualized system include receiving, at a hypervisor from an application executing under a guest OS, a request to write new data to a RAID system, redirecting the request to the VSA owning the RAID drives, moving the new data from guest OS physical address space to VSA physical address space, preparing, by a RAID driver in the VSA, the new data for writing according to a RAID redundancy policy, reading, by the RAID driver into a first buffer, old data and old parity information, performing, by an architectural data mover, inline XOR copy operations to compute a difference between the old and new data, compute new parity information, and write the difference and new parity information into the second buffer, and writing, by the RAID driver, the difference and new parity information to the RAID system using the redundancy policy.
1. A method for input/output acceleration in a virtualized information handling system, comprising:
receiving, at a disk layer of a hypervisor executing in the virtualized information handling system from an application executing under a guest operating system (OS) in a virtual machine, a request to write new data to a redundant array of independent disks (RAID) system comprising a plurality of disk drives;
redirecting the request to a virtualized storage appliance (VSA) that owns the plurality of disk drives;
moving the new data from a physical address space of the guest OS to a physical address space of the virtualized storage appliance;
preparing, by a RAID driver in the virtualized storage appliance, the new data for writing to the RAID system at target addresses in the physical address space of the virtualized storage appliance in accordance with an applicable redundancy policy;
reading, by the RAID driver into a first buffer in a system memory of the virtualized information handling system, old data stored at the target addresses and old parity information associated with the old data;
performing, by an architectural data mover associated with a processor subsystem of the virtualized information handling system, inline exclusive-or (XOR) copy operations to compute a difference between the old data stored in the first buffer and the new data, write the difference into a second buffer in the system memory, compute new parity information based on the difference, and write the new parity information into the second buffer;
writing, by the RAID driver, the difference and the new parity information from the second buffer to the RAID system at the target addresses in the physical address space of the virtualized storage appliance in accordance with the applicable redundancy policy.
2. The method of claim 1 , wherein:
the method further comprises, prior to receiving the request, writing the new data to a third buffer in the system memory; and
the inline exclusive-or (XOR) copy operations are performed using the new data stored in the third buffer and the old data stored in the first buffer.
3. The method of claim 1 , wherein preparing the new data for writing to the RAID system comprises partitioning the new data into multiple data chunks to be written to respective ones of the plurality of disk drives in accordance with a data striping scheme defined by the applicable redundancy policy.
4. The method of claim 1 , wherein:
the architectural data mover is a Peripheral Component Interconnect Express (PCIe) device attached to the processor subsystem using a PCIe driver; and
the method further comprises receiving, by the architectural data mover from the processor subsystem, an instruction to initiate performance of the inline exclusive-or (XOR) copy operations.
5. The method of claim 1 , wherein the architectural data mover resides in the processor subsystem and performs the inline exclusive-or (XOR) copy operations asynchronously and without processor intervention following initiation of the inline exclusive-or (XOR) copy operations by the processor subsystem.
6. The method of claim 1 , wherein the architectural data mover resides outside the processor subsystem and comprises a field programmable gate array (FPGA), application-specific integrated circuit (ASIC), or graphics progressing unit (GPU) programmable by the processor subsystem.
7. The method of claim 1 , wherein the architectural data mover is configured to move data between any two of a virtual address space of the guest OS, the physical address space of the guest OS, a virtual address space of the virtual machine, a physical address space of the virtual machine, a virtual address space of the hypervisor, a physical address space of the hypervisor, a virtual address space of the VSA, and the physical address space of the VSA.
8. The method of claim 1 , wherein the architectural data mover is a Peripheral Component Interconnect Express (PCIe) device comprising respective PCIe functions assigned to two or more of the processor subsystem, the hypervisor, the virtual machine, and the virtualized storage appliance.
9. The method of claim 1 , wherein the applicable redundancy policy defines a data striping scheme including block-level striping of data across multiple ones of the plurality of disk drives and a distribution of parity information across multiple ones of the plurality of disk drives.
10. The method of claim 1 , wherein moving the new data from the physical address space of the guest OS to the physical address space of the virtualized storage appliance is performed by the architectural data mover or by an alternate data mover.
11. An information handling system, comprising:
a processor subsystem; and
a memory subsystem storing program instructions executable by the processor subsystem to implement:
a virtual machine on which an application executes under a guest operating system (OS);
a virtualized storage appliance that owns a plurality of disk drives of a redundant array of independent disks (RAID) system;
a hypervisor configured to:
receive, at a disk layer of the hypervisor from the application, a request to write new data to the RAID system; and
redirect the request to the virtualized storage appliance;
a RAID driver in the virtualized storage appliance configured to:
prepare the new data for writing to the RAID system at target addresses in the physical address space of the virtualized storage appliance in accordance with an applicable redundancy policy; and
read into a first buffer in the memory subsystem, old data stored at the target addresses and old parity information associated with the old data; and
an architectural data mover associated with the processor subsystem and configured to perform inline exclusive-or (XOR) copy operations to compute a difference between the old data stored at the target addresses and the new data, write the difference into a second buffer in the memory subsystem, compute new parity information based on the difference, and write the new parity information into the second buffer;
wherein the RAID driver is further configured to write the difference and the new parity information from the second buffer to the RAID system at the target addresses in the physical address space of the virtualized storage appliance in accordance with the applicable redundancy policy.
12. The information handling system of claim 11 , wherein:
the application is configured to write the new data to a third buffer in the memory subsystem prior to the hypervisor receiving the request; and
the inline exclusive-or (XOR) copy operations are performed using the new data stored in the third buffer and the old data stored in the first buffer.
13. The information handling system of claim 11 , wherein to prepare the new data for writing to the RAID system, the RAID driver is configured to partition the new data into multiple data chunks to be written to respective ones of the plurality of disk drives in accordance with a data striping scheme defined by the applicable redundancy policy.
14. The information handling system of claim 11 , wherein:
the architectural data mover is a Peripheral Component Interconnect Express (PCIe) device attached to the processor subsystem using a PCIe driver; and
the architectural data mover is further configured to receive, from the processor subsystem, an instruction to initiate performance of the inline exclusive-or (XOR) copy operations.
15. The information handling system of claim 11 , wherein the architectural data mover resides in the processor subsystem and is configured to perform the inline exclusive-or (XOR) copy operations asynchronously and without processor intervention following initiation of the inline exclusive-or (XOR) copy operations by the processor subsystem.
16. The information handling system of claim 11 , wherein the architectural data mover resides outside the processor subsystem and comprises a field programmable gate array (FPGA), application-specific integrated circuit (ASIC), or graphics progressing unit (GPU) programmable by the processor subsystem.
17. The information handling system of claim 11 , wherein the architectural data mover is configured to move data between any two of a virtual address space of the guest OS, the physical address space of the guest OS, a virtual address space of the virtual machine, a physical address space of the virtual machine, a virtual address space of the hypervisor, a physical address space of the hypervisor, a virtual address space of the VSA, and the physical address space of the VSA.
18. The information handling system of claim 11 , wherein the architectural data mover is a Peripheral Component Interconnect Express (PCIe) device comprising respective PCIe functions assigned to two or more of the processor subsystem, the hypervisor, the virtual machine, and the virtualized storage appliance.
19. The information handling system of claim 11 , wherein the applicable redundancy policy defines a data striping scheme that includes block-level striping of data across multiple ones of the plurality of disk drives and a distribution of parity information across multiple ones of the plurality of disk drives.
20. The information handling system of claim 11 , further comprising an input/output accelerator implemented in a field programmable gate array (FPGA) and configured to accelerate reading the old data stored at the target addresses and the old parity information associated with the old data into the first buffer.