Storage device, controller and method for operating thereof

1. A storage device comprising:

a semiconductor memory device; and

a controller for controlling the semiconductor memory device,

wherein the controller comprises,

a data updater circuitry controlling so as to update original data stored in an area indicated by an address to first data based on a) the address, b) information on to-be-updated data bits indicating indices of bits in a binary bit stream of the first data at which the original data are to be updated and c) target data for the to-be-updated data bits; and

a parity updater circuitry controlling so as to update original parity for the original data to a target parity, using second data obtained by the parity updater circuitry based on a) the original data and b) first invert indication information,

wherein the first invert indication information is obtained based on a) the information on to-be-updated data bits and b) the target data, the controller calculates the target parity based on the original parity and the second data without further reading all of the original data,

wherein the controller further comprises a first memory device in which the original data is stored,

wherein the data updater circuitry transmits, to the first memory device, the first invert indication information,

wherein the first invert indication information indicates that the first memory device outputs, for each bit of the original data, an inverted value of the bit of the original data when a bit of the first invert indication information corresponding to the bit of the original data is 1 and outputs an original bit value of the bit of the original data when a bit of the first invert indication information corresponding to the bit of the original data is 0,

wherein the first memory device comprises a plurality of memory cells connected to one word line and a plurality of inverting cells included in an inverting cell array and respectively connected to the memory cells,

wherein each inverting cell of the plurality of inverting cells stores therein an inverted value of a value stored in a memory cell, corresponding to the inverting cell, among the plurality of memory cells, and

wherein the first memory device outputs the inverted value from the plurality of inverting cells when a bit of the first invert indication information corresponding to the original bit value is 1 and outputs the original bit value from the plurality of memory cells when a bit of the first invert indication information corresponding to the original bit value is 0.

2. The storage device according to claim 1 ,

wherein the first memory device comprises an input to which the first invert indication information is input, stores the original data in the area, and updates the original data in the area to the first data based on the first invert indication information and outputs the second data.

3. The storage device according to claim 2 ,

wherein BIT and BlTbar lines of the inverting cell and BIT and BlTbar lines of the memory cell corresponding to the inverting cell are reversely connected to each other.

4. The storage device according to claim 3 , wherein the first memory device outputs, according to a value corresponding to one of the to-be-updated data bits in the first invert indication information, one of the value stored in the memory cell and the inverted value stored in the inverting cell as a value corresponding to the one of to-be-updated data bits in the second data.

5. The storage device according to claim 4 , wherein the value corresponding to one of the to-be-updated data bits in the first invert indication information is a value corresponding to one of the to-be-updated data bits in the target data.

6. The storage device according to claim 5 , wherein the value stored in the memory cell is updated to the value corresponding to one of the to-be-updated data bits in the target data.

7. The storage device according to claim 1 ,

wherein the controller further comprises a second memory device in which the original parity is stored,

wherein the parity updater circuitry transmits, to the second memory device, second invert indication information for the target parity, and

wherein the second memory device comprises an input to which the second invert indication information is input, stores the original parity, and updates the original parity to the target parity based on the second invert indication information.

8. The storage device according to claim 7 ,

wherein the second memory device comprises a plurality of memory cells connected to one word line and a plurality of inverting cells respectively connected to the memory cells, and

wherein each of the inverting cells store an inverted value of a value stored in each of the memory cells.

9. The storage device according to claim 8 , wherein the second memory device outputs, according to each bit of the second invert indication information, one of the value stored in the memory cell and the inverted value stored in the inverting cell as the value of the second data corresponding to the to-be-updated data bit.

10. A controller for controlling a semiconductor memory device, the controller comprising:

a data updater circuitry controlling so as to update original data stored in an area of the semiconductor memory device indicated by an address to first data based on a) the address, b) information on the to-be-updated data bits indicating indices of bits in a binary bit stream of the first data at which the original data are to be updated and c) target data for the to-be-updated data bits; and

a parity updater circuitry controlling so as to update original parity for the original data to a target parity, using second data obtained by the parity updater circuitry based on a) the original data and b) first invert indication information,

wherein the first invert indication information is obtained based on a) the information on to-be-updated data bits and b) the target data,

wherein the controller calculates the target parity based on the original parity and the second data without further reading all of the original data,

wherein the controller further comprises a first memory device in which the original data is stored,

wherein the data updater circuitry transmits, to a first memory device, the first invert indication information,

wherein the first invert indication information indicates that the first memory device outputs, for each bit of the original data, an inverted value of the bit of the original data when a bit of the first invert indication information corresponding to the bit of the original data is 1 and outputs an original bit value of the bit of the original data when a bit of the first invert indication information corresponding to the bit of the original data is 0,

wherein the first memory device comprises a plurality of memory cells connected to one word line and a plurality of inverting cells included in an inverting cell array and respectively connected to the memory cells,

wherein each inverting cell of the plurality of inverting cells stores therein an inverted value of a value stored in a memory cell, corresponding to the inverting cell, among the plurality of memory cells, and

wherein the first memory device outputs the inverted value from the plurality of inverting cells when a bit of the first invert indication information corresponding to the original bit value is 1 and outputs the original bit value from the plurality of memory cells when a bit of the first invert indication information corresponding to the original bit value is 0.

11. The controller according to claim 10 ,

wherein the first memory device comprises an input to which the first invert indication information is input, stores the original data in the area, and updates the original data to the first data based on the first invert indication information and calculates the second data.

12. The controller according to claim 11 ,

wherein BIT and BlTbar lines of the inverting cell and BIT and BlTbar lines of the memory cell corresponding to the inverting cell are reversely connected to each other.

13. The controller according to claim 12 , wherein the first memory device outputs, according to a value corresponding to one of the to-be-updated data bits in the first invert indication information, one of the value stored in the memory cell and the inverted value stored in the inverting cell as a value corresponding to the one of to-be-updated data bits in the second data.

14. The controller according to claim 13 , wherein the value corresponding to the one of the to-be-updated data bits in the first invert indication information is a value corresponding to the one of the to-be-updated data bit in the target data.

15. The controller according to claim 10 ,

further comprising a second memory device at which the original parity is stored,

wherein the parity updater circuitry transmits, to the second memory device, second invert indication information for the target parity, and

wherein the second memory device comprises an input to which the second invert information is input, stores the original parity, and updates the original parity to the target parity based on the second invert indication information.

16. The controller according to claim 15 ,

wherein the second memory device comprises a plurality of memory cells connected to one word line and a plurality of inverting cells respectively connected to the memory cells, and

wherein each of the inverting cells store an inverted value of a value stored in each of the memory cells.

17. The controller according to claim 16 , wherein the second memory device outputs, according to each bit of the second invert indication information, one of the value stored in the memory cell and the inverted value stored in the inverting cell as the value of the second data corresponding to the to-be-updated data bit.

18. A method for operating a storage device, the method comprising:

updating original data stored in an area of the storage device indicated by an address to first data based on a) the address, b) information on the to-be-updated data bits indicating indices of bits in a binary bit stream of the first data at which the original data are to be updated and c) target data for the to-be-updated data bits; and

updating original parity for the original data to a target parity, using second data obtained based on a) the original data and b) first invert indication information,

wherein the first invert indication information is obtained based on a) the information on to-be-updated data bits and b) the target data,

wherein the target parity is calculated based on the original parity and the second data without further reading all of the original data,

wherein the original data is updated to the first data based on the first invert indication information and outputs the second data,

wherein the first invert indication information indicates that, for each bit of the original data, an inverted value of the bit of the original data is outputted when a bit of the first invert indication information corresponding to the bit of the original data is 1 and an original bit value of the bit of the original data is outputted when a bit of the first invert indication information corresponding to the bit of the original data is 0,

wherein the original bit value is outputted from a plurality of memory cells storing the original bit value when a bit of the first invert indication information corresponding to the bit of the original data is 0, and

wherein the inverted value is outputted from a plurality of inverting cells, each stores an inverted value of a value stored in a corresponding memory cell among the plurality of memory cells, when a bit of the first invert indication information corresponding to the bit of the original data is 1.

19. The method according to claim 18 , wherein the original parity is updated to the target parity according to second invert indication information obtained from the target parity.