Fabrication method for a 3-dimensional NOR memory array
A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stacks to create corresponding cavities in the active layers; (f) filling the cavities in the active stacks by a metallic or conductor material; (g) recessing the dielectric layer from the exposed sidewalls of the active stacks; and (h) filling recesses in the dielectric layer by a third semiconductor layer of a second conductivity opposite the first conductivity.
1. A process, comprising:
providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity type; (ii) a dielectric layer separating the first and second semiconductor layers; and (ii) one or more sacrificial layers, at least one of the sacrificial layers being adjacent the first semiconductor layer;
etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks;
filling the first set of trenches by a silicon oxide;
patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks;
removing the sacrificial layers from the exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stacks to create cavities in the active layers;
filling the cavities in the active stacks by a metallic or conductor material;
recessing the dielectric layer from the exposed sidewalls of the active stacks; and
filling recesses in the dielectric layer by a third semiconductor layer of a second conductivity opposite the first conductivity.
2. The process of claim 1 , wherein adjacent active layers are separated by an isolation layer.
3. The process of claim 1 , further comprising recessing the metallic or conductor layer from the exposed sidewalls of the active stacks, wherein filling recesses in the dielectric layer also fills recesses in the metallic or conductor material.
4. The process of claim 1 , further comprising:
removing the silicon oxide columns prior to recessing the dielectric layer and
re-creating the silicon oxide columns after filling the recesses in the dielectric layer by the third semiconductor layer.
5. The process of claim 1 , further comprising providing a charge storsge material over the exposed sidewalls of the active stack.
6. The process of claim 1 , further comprising forming word lines by filling spaces surrounded by adjacent silicon oxide columns and the active stacks with a conductor material.
7. The process of claim 6 , wherein the third semiconductor layer comprises an in situ boron-doped polysilicon.
8. The process of claim 7 , wherein (i) the first and second semiconductor layers of each active layer respectively form a common drain region and a common drain region of a plurality of storage transistors organized as a NOR memory string; (ii) the third semiconductor layer forms channel regions of the storage transistors in the NOR memory string; and (iii) the word lines form gate electrodes of the storage transistors in the NOR memory string.
9. A process, comprising:
(i) providing a first active layer;
(ii) providing a first isolation layer on top of the first active layer;
(iii) providing a second active layer on top of the first isolation layer, wherein the first and second active layers each comprise (a) a first semiconductor layer of a first conductivity type ; (b) a dielectric layer of an insulative material underneath the first semiconductor layer; and (c) a second semiconductor layer underneath the dielectric layer;
(iv) providing a second isolation layer on top of the second active layer;
(iv) providing and patterning a photoresist layer over the second isolation layer to create an opening in the photoresist layer, thereby exposing a first area of the second isolation layer;
(v) anisotropically removing the exposed first area of the second isolation layer and the portion of the second active layer under the first area of the second isolation layer so as to expose a first area of the first isolation layer;
(vi) recessing the photoresist layer to increase the opening in the photoresist layer, such that a second area of the second isolation layer is exposed;
(vii) anisotropically removing (a) the exposed first area of the first isolation layer and the exposed second area of the second isolation area, and (ii) the portions of the first semiconductor layer underneath the exposed first area of the first isolation layer and the exposed second area of the second isolation area;
(viii) filling cavities created by the anisotropically removing steps of (v) and (vii), using the insulative material;
(ix) repeating steps (i) through (viii) a predetermined number of times; and
(x) anisotropically removing the insulative material at predetermined locations to create via openings to reach the first semiconductor layer of two or more active layers.