Integrated circuit that extracts data, neural network processor including the integrated circuit, and neural network device

1. An integrated circuit included in a device for performing a neural network operation, the integrated circuit comprising:

a buffer configured to store feature map data in units of cells each comprising at least one feature, each of the at least one feature of each cell corresponding to a coordinate value, wherein the feature map data is for use in the neural network operation; and

a multiplexing circuit including at least one multiplexer, the multiplexing circuit being configured to

receive the feature map data from the buffer,

extract feature data from each cell, the at least one multiplexer being configured to extract each of the at least one feature of each cell corresponding to an identical coordinate value, and

output the extracted feature data.

2. The integrated circuit of claim 1 , wherein the multiplexing circuit is configured to generate first data by extracting, from a plurality of the cells, pieces of feature data corresponding to all coordinate values of the first data, and generate the extracted feature data by rotating the first data in at least one of a vertical direction and a horizontal direction.

3. The integrated circuit of claim 1 , wherein the multiplexing circuit comprises:

a first multiplexing circuit comprising the at least one multiplexer for extracting feature data of one of features included in a plurality of the cells and each corresponding to a first coordinate value, and configured to output first data based on the extracted feature data; and

a second multiplexing circuit comprising a plurality of multiplexers for receiving the first data from the first multiplexing circuit and rotating the first data in a vertical direction or a horizontal direction.

4. The integrated circuit of claim 3 , wherein the first multiplexing circuit comprises a plurality of multiplexers configured to select one input signal from among input signals, a number of which corresponds to the number of the cells included in the feature map data.

5. The integrated circuit of claim 4 , wherein the first multiplexing circuit comprises multiplexers, the number of which corresponds to the number of the at least one feature included in each cell.

6. The integrated circuit of claim 3 , wherein the second multiplexing circuit comprises:

a vertical rotation circuit configured to rotate the first data in the vertical direction by changing an order of rows of the first data in a matrix form, and generate vertically rotated first data; and

a horizontal rotation circuit configured to rotate the vertically rotated first data in the horizontal direction by changing an order of columns of the vertically rotated first data, and generate the extracted feature data.

7. The integrated circuit of claim 6 , wherein

the vertical rotation circuit comprises multiplexers, a number of which corresponds to the number of the rows of the first data, and

the horizontal rotation circuit comprises multiplexers, a number of which corresponds to the number of the columns of the first data.

8. The integrated circuit of claim 7 , wherein

the multiplexers included in the vertical rotation circuit are configured to select different rows of the rows of the first data, respectively, and

the multiplexers included in the horizontal rotation circuit are configured to select different columns of the columns of the first data, respectively.

9. The integrated circuit of claim 1 , wherein

the neural network operation comprises a convolution operation,

the feature map data comprises input feature map data on which the convolution operation is to be performed, and

the extracted feature data is data that is to be directly multiplied by a weight during the convolution operation.