Workload placement using conflict cost

1. A system comprising:

at least one computing device comprising at least one processor and at least one data store;

instructions stored in the at least one data store, wherein the instructions, when executed by the at least one processor, cause the at least one computing device to at least:

identify a protected memory level for a computing environment comprising a scheduling service that assigns processor workloads to a plurality of processor resources corresponding to the protected memory level, wherein incompatible processor workloads are prohibited-from concurrently executing on parallel processor resources that share a memory at the protected memory level, the protected memory level specifying a memory type corresponding to: a level one cache, a level two cache, a level three cache, a last level cache, a non-uniform memory access (NUMA)-shared memory or a uniform memory access (UMA)-shared memory;

determine a plurality of conflict costs for a processor workload, a respective conflict cost corresponding to a respective processor resource of the plurality of processor resources, the respective conflict cost being determined based on a measure of compatibility between the processor workload and a parallel processor resource that shares, at the protected memory level, a particular memory with the respective processor resource; and

assign the processor workload to execute on a processor resource associated with a minimum conflict cost of the plurality of conflict costs.

2. The system of claim 1 , wherein the measure of compatibility is determined based on existing workloads assigned to execute on the parallel processor resource.

3. The system of claim 1 , wherein the protected memory level is associated with protection of at least one of: level one caches, level two caches, level three caches, uniform memory access (UMA) memories, and non-uniform memory access (NUMA) memories.

4. The system of claim 1 , wherein the plurality of processor resources comprise at least one of: threads that share level one caches, cores that share last level caches, processors that share UMA memories, and processors that share NUMA memories.

5. The system of claim 1 , wherein the instructions, when executed by the at least one processor, cause the at least one computing device to at least:

tag a plurality of processor workloads with a corresponding plurality of workload tags, wherein processor workloads tagged with differing workload tags are incompatible, and processor workloads tagged with matching workload tags are compatible.

6. The system of claim 1 , wherein the respective conflict cost is determined using a difference between an unconflicted load of the processor workload and an actual load of the processor workload when assigned to execute on the processor resource, the actual load being determined based on the measure of compatibility between the processor workload and the parallel processor resource.

7. The system of claim 1 , wherein the instructions, when executed by the at least one processor, cause the at least one computing device to at least:

determine that the computing environment is overcommitted based on a number of processor workloads exceeding a number of the processor resources that share memories at the protected memory level.

8. A method comprising:

identifying a protected memory level for a computing environment comprising a scheduling service that assigns processor workloads to a plurality of processor resources at the protected memory level, wherein incompatible processor workloads are prohibited from concurrently executing on parallel processor resources that share a memory at the protected memory level, the protected memory level specifying a memory type corresponding to: a level one cache, a level two cache, a level three cache, a last level cache, a non-uniform memory access (NUMA)-shared memory or a uniform memory access (UMA)-shared memory;

determining a plurality of conflict costs for a processor workload, a respective conflict cost corresponding to a respective processor resource of the plurality of processor resources, the respective conflict cost being determined based on a measure of compatibility between the processor workload and a parallel processor resource that shares, at the protected memory level, a particular memory with the respective processor resource; and

assigning the processor workload to execute on a processor resource associated with a minimum conflict cost of the plurality of conflict costs.

9. The method of claim 8 , wherein the measure of compatibility is determined based on existing workloads assigned to execute on the parallel processor resource.

10. The method of claim 8 , wherein the protected memory level is associated with protection of at least one of: level one caches, level two caches, last level caches, uniform memory access (UMA) memories, and non-uniform memory access (NUMA) memories.

11. The method of claim 8 , wherein the plurality of processor resources comprise at least one of: threads that share level one caches, cores that share last level caches, processors that share UMA memories, and processors that share NUMA memories.

12. The method of claim 8 , further comprising:

tagging a plurality of processor workloads with a corresponding plurality of workload tags, wherein processor workloads tagged with differing workload tags are incompatible.

13. The method of claim 8 , wherein the respective conflict cost is determined using a difference between an unconflicted load of the processor workload and an actual load of the processor workload when assigned to execute on the processor resource, the actual load being determined based on the measure of compatibility between the processor workload and the parallel processor resource.

14. The method of claim 8 , further comprising:

determining that the computing environment is overcommitted based on a number of processor workloads exceeding a number of the processor resources that share memories at the protected memory level.

15. A non-transitory computer-readable medium comprising machine readable instructions, wherein the instructions, when executed by at least one processor, cause at least one computing device to at least:

identify, by a scheduling service, a protected memory level for a computing environment comprising a plurality of processor resources at the protected memory level, the protected memory level indicating a memory type corresponding to: a level one cache, a level two cache, a level three cache, a last level cache, a non-uniform memory access (NUMA)-shared memory or a uniform memory access (UMA)-shared memory;

prohibit, by the scheduling service, a processor workload from executing on parallel processor resources that share a memory at the protected memory level, wherein at least one of the parallel processor resources executes an incompatible processor workload that is incompatible with the processor workload; and

assign, by the scheduling service, the processor workload to execute on a processor resource selected from a subset of the plurality of processor resources that excludes the parallel processor resources that are prohibited for the processor workload.

16. The non-transitory computer-readable medium of claim 15 , wherein a measure of compatibility is determined based on existing workloads assigned to execute on a parallel processor resource that is parallel to the processor resource.

17. The non-transitory computer-readable medium of claim 15 , wherein the protected memory level is associated with protection of at least one of: level one caches, level two caches, level three caches, uniform memory access (UMA) memories, and non-uniform memory access (NUMA) memories.

18. The non-transitory computer-readable medium of claim 15 , wherein the plurality of processor resources comprise at least one of: threads that share level one caches and level two caches, cores that share level three caches, processors that share UMA memories, and processors that share NUMA memories.

19. The non-transitory computer-readable medium of claim 15 , wherein the instructions, when executed by the at least one processor, cause the at least one computing device to at least:

tag a plurality of processor workloads with a corresponding plurality of workload tags, wherein processor workloads tagged with differing workload tags are incompatible.

20. The non-transitory computer-readable medium of claim 15 , wherein the instructions, when executed by the at least one processor, cause the at least one computing device to at least:

determine a respective conflict cost for a respective processor resource of the plurality of processor resources using a difference between an unconflicted load of the processor workload and an actual load of the processor workload when assigned to execute on the respective processor resource.