IP Library Granted Patent US 11,031,959
Granted Patent B1
US 11,031,959 · App. 16/513,447 · Granted Jun 8, 2021

System and method for informational reduction

Inventor: Allan Havemose (Arroyo Grande, CA)
Assignee: OPEN INVENTION NETWORK LLC
H03M13/6318G06F11/1076H03M13/05
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Quick Facts
Patent No.
US 11,031,959
App. No.
16/513,447
Granted
Jun 8, 2021
Kind
B1
Abstract

Information reduction in data processing environments includes at least one of: one or more Error Correcting Codes that decode n-vectors into k-vectors and utilize said decoding to information-reduce data from a higher dimensional space into a lower dimensional space. The information reduction further provides for a hierarchy of information reduction allowing a variety of information reductions. Transformations are provided to utilize available data space, and data may be transformed using several techniques including windowing functions, filters in the time and frequency domains, or any numeric processing on the data.

Claims (24)

1. A system, comprising:

one or more memory locations configured to store one or more Error Correcting Code ECC(n,k) of length n and dimension k, where n>k, and vectors of length n (n-vector); and

one or more Central Processing Unit (CPU) operatively connected to said one or more memory locations and configured to decode said n-vector using said ECC(n,k) to generate a k-vector and store said k-vector in the one or more memory locations.

2. The system according to claim 1 , wherein said CPU execute said one or more ECC(n,k) on a host with a host operating system that is one of Linux, UNIX, Solaris, HP/UX, Android, iOS, MacOS, or Microsoft Windows.

3. The system according to claim 1 , wherein one or more pairs of (n-vector, k-vector) are stored in one of said second memory locations, and wherein a pair's k-vector is an information-reduced representation of the pair's n-vector.

4. The system according to claim 1 , wherein said ECC(n,k) reduces the n-dimensional n-vector to a k-dimensional k-vector, and said ECC(n,k) is one or more of a linear error correcting code and a Maximum Separable (MDS) error correcting code.

5. The system according to claim 1 , wherein said ECC(n,k) is an error correcting code with a minimum distance d.

6. The system according to claim 1 , wherein said ECC(n,k) is one of a Reed-Solomon (RS) error code, a Bose, Ray-Chaudhuri, Hocquenghem (BCH) error correcting code, Golay error correction code, Hamming error correcting code, convolution code, other error correcting code of length n with dimension k.

7. The system according to claim 1 , wherein said n-vectors and said k-vectors are comprised of elements from a finite field F.

8. The system according to claim 7 , wherein said finite field F has a number of elements that is a power of 2.

9. The system according to claim 1 , wherein said ECC is implemented as one or more of an application, one or more processes and threads, a device driver, a kernel module, a kernel extension, a plug-in, or other software implementation.

10. The system according to claim 1 , wherein each n-vector is transformed prior to information reduction using a windowing function.

11. The system according to claim 10 , where said windowing function is one of rectangular, triangular, Parzen, Welch, Hamming and Generalized Hamming, Hann, or other Windowing function.

12. The system according to claim 1 , wherein each n-vector is transformed prior to information reduction using an inverse Fisher transform.

13. The system according to claim 1 , wherein each n-vector is transformed prior to information reduction as pre-processing for one or more of speech recognition, voiceprints, optical character recognition, or other biometrics.

14. The system according to claim 1 , wherein each n-vector is transformed prior to information reduction as pre-processing for a search application, or other alphanumeric processing application.

15. A system, comprising:

one or more memory locations configured to store one or more Error Correcting Code ECC i of length n i and dimension k i configured as n i -vectors and k i -vectors, where i=1 . . . m, m>=1, and n i >k i ; and

one or more Central Processing Unit (CPU) operatively connected to said one or more memory locations and configured to decode said n-vector using said ECC(n,k) to generate a k i -vector and stores said k i -vector in the one or more memory locations.

16. The system according to claim 15 , wherein said host operating system is one of Linux, UNIX, Solaris, HP/UX, Android, iOS, MacOS, or Microsoft Windows.

17. The system according to claim 15 , wherein each said ECC i is one or more of linear error correcting code, Convolution error correcting code, and a Maximum Separable (MDS) error correcting code.

18. The system according to claim 15 , wherein each said ECC i is one of a Reed-Solomon (RS) error code, a Bose, Ray-Chaudhuri, Hocquenghem (BCH) error correcting code, Golay error correction code, Hamming error correcting code, and other error correcting code of length n i with dimension k i .

19. The system according to claim 15 , wherein each said n i -vectors and said k i -vector are comprised of elements from a finite field F.

20. The system according to claim 15 , wherein each said ECC i is implemented as one or more of an application, one or more processes and threads, a device driver, a kernel module, a kernel extension, a plug-in, or other software implementation.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2021
From: OPEN INVENTION NETWORK LLC
To: PHILIPS NORTH AMERICA LLC
Reel/Frame 058600/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2021
From: HAVEMOSE, ALLAN
To: OPEN INVENTION NETWORK LLC
Reel/Frame 057152/0863 →