Spectrum monitoring

1. A computing system, comprising:

a set of analog-to-digital converters (ADCs) configured to receive a time-domain representation of a signal and generate an output signal;

a segment controller configured to:

segment the output signal into a plurality of segments,

determine a center frequency for a segment of the plurality of segments,

determine a segment bandwidth for the segment based at least in part on a sampling frequency associated with the set of analog-to-digital converters, a number of segments included in the plurality of segments, and a resolution mode, and

apply the center frequency of the segment to a digital mixer;

the digital mixer configured to translate a frequency associated with the segment to a baseline frequency to generate a translated signal segment based at least in part on the center frequency;

a decimation filter configured to adjust a rate of the translated signal segment based at least in part on a determined resolution mode to generate an adjusted translated signal segment;

a spectral analysis component configured to generate a frequency-domain representation of the adjusted translated signal segment; and

a power component configured to generate power spectral information for the frequency-domain representation of the adjusted translated signal segment, wherein the power spectral information for a plurality of frequency-domain representations of the plurality of segments is stored.

2. The computing system of claim 1 , wherein the spectral analysis component when configured to generate the frequency-domain representation of the adjusted translated signal segment is further configured to:

use a fast Fourier transform technique on the adjusted translated signal segment to generate the frequency-domain representation of the adjusted translated signal segment.

3. The computing system of claim 1 , wherein the segment controller is further configured to:

determine a start frequency for individual segments of the plurality of segments based at least in part on a number of segments of the plurality of segments and the segment bandwidth.

4. The computing system of claim 3 , wherein the segment controller is further configured to:

determine the center frequency for the segment based at least in part on the start frequency, the segment bandwidth, and a segment position of the segment.

5. The computing system of claim 1 , further comprising:

a filter component configured to filter the translated signal segment, wherein the filter component includes at least the decimation filter.

6. The computing system of claim 5 , wherein the filter component is programmable, and wherein a decimation rate of the filter component is programmed based at least in part on a resolution mode.

7. The computing system of claim 1 , further comprising:

a buffer component configured to buffer a plurality of translated signal segments obtained from a filter component, wherein individual buffered translated signal segments are processed by the spectral analysis component.

8. The computing system of claim 1 , further comprising:

an averaging component configured to average the power spectral information for the plurality of segments.

9. The computing system of claim 1 , wherein the computing system is implemented on a chip.

10. An apparatus, comprising:

a set of analog-to-digital converters (ADCs);

at least one computing device processor; and

a memory device including instructions that, when executed by the at least one computing device processor, enables the at least one computing device processor to:

process a time-domain representation of a communications signal to generate a digital representation of the communications signal,

segment the digital representation of the communications signal into a plurality of segments,

determine a center frequency for a segment of the plurality of segments,

determine a segment bandwidth for the segment based at least in part on a sampling frequency associated with the set ADCs, a number of segments included in the plurality of segments, and a resolution mode,

translate a frequency associated with the segment to a baseline frequency to generate a translated signal segment based at least in part on the center frequency,

use a spectral analysis technique on the translated signal segment to generate a frequency-domain representation of the translated signal segment

determine a power spectral information for the frequency-domain representation of the segment, and

store the power spectral information for a plurality of frequency-domain representations of the plurality of segments.

11. The apparatus of claim 10 , wherein the instructions when executed by the at least one computing device processor further enable the at least one computing device processor to:

use a fast Fourier transform technique on the translated signal segment to generate the frequency-domain representation of the translated signal segment.

12. The apparatus of claim 10 , wherein the instructions when executed by the at least one computing device processor further enable the at least one computing device processor to:

determine a start frequency for individual segments of the plurality of segments based at least in part on a number of segments of the plurality of segments and the segment bandwidth.

13. The apparatus of claim 12 , wherein the instructions when executed by the at least one computing device processor further enable the at least one computing device processor to:

determine the center frequency for the segment based at least in part on the start frequency, the segment bandwidth, and a segment position of the segment.

14. The apparatus of claim 10 , wherein the instructions when executed by the at least one computing device processor further enable the at least one computing device processor to:

program a filter component based at least in part on a resolution mode; and

filter the translated signal segment.

15. The apparatus of claim 10 , wherein the instructions when executed by the at least one computing device processor further enable the at least one computing device processor to:

buffer a plurality of translated signal segments obtained from a filter component; and

process individual buffered translated signal segments by a spectral analysis component.

16. A method, comprising:

processing a time-domain representation of a communications signal to generate a digital representation of the communications signal;

segmenting the digital representation of the communications signal into a plurality of segments;

determining a center frequency for a segment of the plurality of segments,

determining a segment bandwidth for the segment based at least in part on a sampling frequency associated with a set of analog-to-digital converters, a number of segments included in the plurality of segments, and a resolution mode,

translating a frequency associated with the segment to a baseline frequency to generate a translated signal segment based at least in part on the center frequency;

using a spectral analysis technique on the translated signal segment to generate a frequency-domain representation of the translated signal segment;

determining a power spectral information for the frequency-domain representation of the segment; and

storing the power spectral information for a plurality of frequency-domain representations of the plurality of segments.

17. The method of claim 16 , further comprising:

obtaining information for a resolution mode; and

programming a decimation filter with a decimation rate based at least in part on the resolution mode.

18. The method of claim 16 , further comprising:

filtering the translated signal segment;

buffering the translated signal segment;

using a fast Fourier transform technique on the translated signal segment to generate the frequency-domain representation of the translated signal segment; and

averaging the power spectral information for the frequency-domain representation of the translated signal segment.