Maximum likelihood error detection for decision feedback equalizers with PAM modulation
The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.
1. An error detection device comprising:
a decision feedback equalizer (DFE) configured to remove intersymbol interference (ISI) noise from a data signal and generate DFE decisions;
a signal processor for removing reflection noise from the DFE decisions; and
an error detector configured to detect error events associated with a sequence of data of the DFE decisions by performing maximum likelihood detections, the error detector being configured to store signs associated with an input error state and generate an output error states by flipping the signs.
2. The device of claim 1 further comprising a feedforward equalizer (FFE) configured to equalize the data signal.
3. The device of claim 1 wherein the error detector removes burst errors associated with the DFE decisions.
4. The device of claim 1 wherein the error detector implements a reduced-state trellis path.
5. The device of claim 1 wherein the data signal comprises pulse-amplitude modulation (PAM)-4 data.
6. The device of claim 1 further comprising a de-mapping module for processing the data signal.
7. The device of claim 1 wherein the error events are associated with Nyquist error events.
8. The device of claim 1 further comprising an enable logic configured to generate a control signal for the error detector based on a quality of the data signal.
9. An input terminal for receiving a data signal comprising,
a decision feedback equalizer (DFE) configured to remove intersymbol interference (ISI) noise from a data signal and generate DFE decisions;
an error generator configured to generate an error signal by comparing the data signal and the DFE decisions; and
an error detector configured to detect error by analyzing the DFE decisions and the error signal using a reduced-state trellis path, the error detector being configured to store signs associated with an input error state and generate an output error states by flipping the signs.
10. The device of claim 9 wherein the error detector comprises a maximum likelihood sequence detection module.
11. The device of claim 9 wherein the error generator subtracts DFE decisions from the data signal.
12. The device of claim 9 further comprising a feedforward equalizer for equalizing the data signal,
wherein the error generator compares the equalized data signal and the DFE decisions.
13. The device of claim 9 wherein the reduced-state trellis path comprises an input zero state and the input error state.
14. The device of claim 9 wherein the reduced-state trellis path comprises an output zero state and the output error state.
15. A communication device comprising:
an input terminal for receiving a data signal;
a decision feedback equalizer (DFE) configured to remove intersymbol interference (ISI) noise from a data signal and generate DFE decisions;
an error detector configured to detect error events associated with the DFE decisions by performing maximum likelihood detections, the error detector being configured to store signs associated with an input error state and generate an output error states by flipping the signs;
a de-mapping module for de-mapping the data signal;
a forward error correction (FEC) decoder for decoding the de-mapped data signal using at least the DFE decisions.
16. The device of claim 15 further comprising a feedforward equalizer (FFE) configured to equalize the data signal that amplifies an amplitude of the data signal by a predetermined amount.
17. The device of claim 16 further comprising slicer coupled to the FFE.
18. The device of claim 15 wherein the de-mapping module is coupled to the FEC decoder.
19. The device of claim 15 further comprising a controller coupled to the DFE.
20. The device of claim 15 further comprising an enable logic configured to
generate a control signal for the error detector based on a quality of the data signal.