Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory
A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
1. A semiconductive device stack, comprising:
a baseband processor die including an active surface and a backside surface;
a recess disposed in the backside surface;
a recess-seated die disposed in the recess;
a through-silicon via (TSV) in the baseband processor die that couples the active surface to the recess-seated die at the recess; and
a processor die disposed on the baseband processor die backside surface, wherein the processor die is coupled to the baseband die through a TSV at, the backside surface.
2. The semiconductive device stack of claim 1 , further including:
a memory die disposed on the processor die, wherein the processor die and the memory die communicate through a TSV in the processor die.
3. The semiconductive device stack of claim 1 , further including:
a memory die disposed on the processor die, wherein the processor die and the memory die communicate through a TSV in the processor die;
a redistribution layer (RDL) disposed on the active surface;
a ball-grid array disposed on the RDL; and
a package substrate coupled to the ball-grid array.
4. The semiconductive device stack of claim 1 , wherein the recess is a first recess. wherein the TSV is part of a first TSV group, further including:
a redistribution layer (RDL) disposed on the active surface;
a subsequent recess disposed in the backside surface;
a subsequent recess-seated device disposed in the subsequent recess;
a subsequent TSV group in the baseband processor die that couples the baseband processor die at the active surface to the subsequent recess-seated die at the subsequent recess;
a ball-grid array disposed on the RDL; and
a package substrate coupled to the ball-grid array.
5. The semiconductive device stack of claim 1 , further including:
wherein the TSV is part of a first TSV group, and wherein the processor die also is coupled to a first lateral TSV group that is disposed in the baseband processor die.
6. The semiconductive device stack of claim 1 , further including:
wherein the TSV is part of a first TSV group, and wherein the processor die also is coupled to a first lateral TSV group that is disposed in the baseband processor die; and
a memory die disposed on the processor die, wherein the processor die and the memory die communicate through a TSV in the processor die.
7. The semiconductive device stack of claim 1 , wherein the recess is a first recess, wherein the TSV is part of a first TSV group, further including:
a subsequent recess disposed in the backside surface;
a subsequent recess-seated die disposed in the subsequent recess; and
a subsequent TSV group in the baseband processor die that couples the baseband processor die at the active surface to the subsequent recess-seated die at the subsequent recess, wherein the first TSV group has a first height, the subsequent. TSV group has a subsequent height, and wherein the first height and subsequent height are not equal.
8. The semiconductive device stack of claim 7 , wherein the processor die also is coupled to a first lateral TSV group that is disposed in the baseband processor die.
9. The semiconductive device stack of claim 1 , further including:
a processor die disposed on the baseband processor die backside surface, wherein the processor die is coupled to the baseband die through the TSV;
wherein the TSV is part of a first TSV group, and wherein the processor die also is coupled to a first lateral TSV group that is disposed in the baseband processor die; and
a memory die disposed on the processor die. erein the processor die and the memory die coir municate through a TSV in the processor die.
10. A process of forming a monolithic die stack, comprising:
forming a first recess in a baseband processor die backside surface, wherein the baseband processor die includes an active surface opposite the die backside;
seating a first recess-seated die in the first recess, wherein the first recess-seated die is coupled to the active surface by a through-silicon via (TSV);
mounting a processor die on the baseband die backside surface, wherein the processor die is coupled to the active surface by a first lateral TSV; and
mourning a memory die on the processor die, wherein the memory die is coupled to the processor die by a first processor die TSV.
11. The process of claim 10 , further including assembling a redistribution layer (RDL) to the baseband processor die active surface.
12. The process of claim 10 , further including:
assembling a redistribution layer (RDL) to the baseband processor die active surface;
assembling an electrical bump array to the RDL; and
assembling a package substrate to the monolithic die stack.
13. The process of claim 10 , furher including seating a first recess-stacked die on the first recess-seated die.
14. The process of claim 10 , further including:
forming a subsequent recess in the baseband processor die backside surface, wherein the subsequent recess and the first recess are separately formed through the baseband processor die backside surface; and
seating a subsequent recess-seated die in the subsequent recess.
15. The process of claim 10 , further including seating a first recess-stacked die on the first recess-seated die.
16. The process of claiiri 10 , further including mounting a die face-to-face on the processor die.
17. The process of claim 10 , wherein forming the recess includes etching selected from the group consisting of reactive-ion etching and wet etching.
18. A computing system using a semiconductive device stack, comprising:
a baseband processor die including an active surface and a backside surface;
a first recess disposed in the backside surface;
a first recess-seated die disposed in the first recess; and
a through-silicon via (TSV) in the baseband processor die that couples the baseband processor die at the active surface to the recess-seated die at the recess;
a redistribution :layer (RDL) coupled to the active surface;
an electrical bump array coupled to the RDL; and
a package substrate coupled to the electrical bump array.
19. The computing system of claim including a physical shell coupled to the package substrate.
20. The computing system of claim 18 , further including:
a processor die disposed on the baseband processor die backside surface, wherein the processor die is coupled to the baseband die through a TSV on the backside surface; and
a memory die disposed on the processor die, wherein the processor die and the memory die communicate through a TSV in the processor die.
21. The computing system of claim 20 , wherein the recess is a first recess, wherein the TSV is part of a first TSV group, further including:
a subsequent recess disposed in the backside surface;
a subsequent recess-seated die disposed in the subsequent recess; and
a subsequent TSV group in the baseband processor die that couples the baseband processor die at the active surface to the subsequent recess-seated die at the subsequent recess.
22. A serniconductive device stack, comprising:
a baseband processor die including an active surface and a backside surface;
a recess disposed in the backside surface;
a recess-seated die disposed in the recess;
a through-silicon via (TSV) in the baseband processor die that couples the active surface to the recess-seated die at the recess; and
a processor die disposed on the baseband processor die backside surface, wherein the processor die is coupled to the baseband die through a TSV at the backside surface.
23. The semiconductive device stack of claim 22 , further including:
a memory die disposed on the processor die, wherein the processor die and the memory die communicate through a TSV in the processor die.
24. The semiconductive device stack of claim 22 , further including:
a memory die disposed on the processor die, wherein the processor die and the memory die communicate through a TSV in the processor die;
a redistribution layer (RDL) disposed on the active surface;
a ball-grid array disposed on the RDL; and
a package substrate coupled to the ball-grid array.
25. The semiconductive device stack of claim 22 , wherein the recess is a first recess, wherein the TSV is part of a first TSV group, further including:
a redistribution layer (RDL) disposed on the active surface;
a subsequent recess disposed in the backside surface;
a subsequent recess-seated die disposed in the subsequent recess;
a subsequent TSV group in the baseband processor die that couples the baseband processor die at the active surface to the subsequent recess-seated die at the subsequent recess;
a ball-grid array disposed on the RDL; and
a package substrate coupled to the ball-grid array.