IP Library Granted Patent US 10,943,669
Granted Patent B2
US 10,943,669 · App. 16/519,445 · Granted Mar 9, 2021

Memory system and method for optimizing read threshold

Inventors: Fan Zhang (San Jose, CA); Yu Cai (San Jose, CA); Chenrong Xiong (San Jose, CA); Xuanxuan Lu (San Jose, CA)
Assignee: SK hynix Inc.
G11C29/38G06F3/0619G06F3/0659G06F3/0673
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Quick Facts
Patent No.
US 10,943,669
App. No.
16/519,445
Granted
Mar 9, 2021
Kind
B2
Abstract

A memory system includes a memory device and a controller. The controller performs a test read operation on a read data set of the memory device, using multiple read threshold entries and determines which are good read threshold entries based on results of the read operation. The controller selects a best read threshold entry among the multiple read threshold entries based on a result of the test read operation, partitions the read data set into a good data set decodable by the best read threshold entry and a bad data set undecodable by the best read threshold entry, and sets the bad data set as a new read data set.

Claims (28)

1. A memory system comprising:

a memory device; and

a controller suitable for:

performing a test read operation on a read data set of the memory device, using multiple read threshold entries; and

determining good read threshold entries among the multiple read threshold entries based on results of the test read operation,

wherein the determining of the good read threshold entries includes:

selecting a best read threshold entry among the multiple read threshold entries, each of which is associated with a failure indicator, based on a result of the test read operation, wherein the best read threshold entry has the lowest failure indicator;

partitioning the read data set into a good data set that includes data in the read data set that is decodable by the best read threshold entry and a bad data set that includes data in the read data set that is undecodable by the best read threshold entry; and

setting the bad data set as a new read data set on which a test read operation is performed using the multiple read threshold entries excluding the best read threshold entry,

wherein the determining, selecting and partitioning operations are repeated with respect to the new read data set.

2. The memory system of claim 1 , wherein the result of the test read operation includes numbers of fail bits for the read data set.

3. The memory system of claim 1 , wherein the read data set corresponds to physical addresses selected from a super block of the memory device.

4. The memory system of claim 1 , further comprising:

performing a normal read operation on the memory device in response to a read command from a host, using the good read threshold entries.

5. The memory system of claim 1 , wherein individual reads of the test read operation are interleaved with individual reads of a normal read operation.

6. A method for operating a memory system which includes a memory device, the method comprising:

performing a test read operation on a read data set of the memory device, using multiple read threshold entries; and

determining good read threshold entries among the multiple read threshold entries based on results of the test read operation,

wherein the determining of the good read threshold entries includes:

selecting a best read threshold entry among the multiple read threshold entries, each of which is associated with a failure indicator, based on a result of the test read operation, wherein the best read threshold entry has the lowest failure indicator;

partitioning the read data set into a good data set that includes data in the read data set that is decodable by the best read threshold entry and a bad data set that includes data in the read data set that is undecodable by the best read threshold entry; and

setting the bad data set as a new read data set on which a test read operation is performed using the multiple read threshold entries excluding the best read threshold entry,

wherein the determining, selecting and partitioning operations are repeated with respect to the new read data set.

7. The method of claim 6 , wherein the result of the test read operation includes numbers of fail bits for the read data set.

8. The method of claim 6 , wherein the read data set corresponds to physical addresses selected from a super block of the memory device.

9. The method of claim 6 , further comprising:

performing a normal read operation on the memory device in response to a read command from a host, using the good read threshold entries.

10. The method of claim 6 , wherein individual reads of the test read operation are interleaved with individual reads of a normal read operation.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2019
From: SK HYNIX MEMORY SOLUTIONS AMERICA INC.
To: SK HYNIX INC.
Reel/Frame 050735/0023 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2019
From: ZHANG, FAN; CAI, YU; XIONG, CHENRONG; LU, XUANXUAN
To: SK HYNIX MEMORY SOLUTIONS AMERICA INC.
Reel/Frame 050063/0602 →
Continuity (2)
Provisional Application 62702082 · Jul 23, 2018
Related Publication 20200027519A1 · Jan 23, 2020
Cited By (1)
US 12,451,198