Fast protection switching in distributed systems

1. A method of switching timing cards, comprising:

receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card;

receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card;

producing a clock signal from the first pulse-width modulated clock signal;

switching to producing the clock signal from the second pulse-width modulated clock signal based on the information encoded in the first pulse-width modulated clock signal; and

providing a GPIO output signal from data received on one or more of the first pulse-width modulated clock signal and the second pulse-width modulated clock signal.

2. The method of claim 1 , wherein the information regarding the status of the first line card includes one or more of loss of signal, loss of connection, and frequency offset.

3. A timing card, comprising:

a plurality of demodulators, each of the plurality of demodulators receiving a pulse-width modulated clock signal from a corresponding line card and recovering data encoded in the pulse-width modulation of the pulse-width modulated clock signal;

a multiplexer coupled to the plurality of demodulators, the multiplexer receiving a clock signal from each of the plurality of demodulators, the clock signal corresponding to the received pulse-width modulated clock signal received at each demodulator;

a controller coupled to the plurality of demodulators to receive the data encoded in each of the pulse-width modulated clock signal, and further coupled to the multiplexer to provide a signal selecting one of the clock signals;

a phase-locked loop that receives the selected one of the clock signals from the multiplexer and provides an output clock signal; and

an output GPIO signal based on the data received from the plurality of demodulators.

4. The timing card of claim 3 , wherein the controller controls the multiplexer to switch between clock signals received from the plurality of demodulators based on data received from the plurality of demodulators.

5. A line card, comprising:

a phase-locked loop that receives a clock signal, the phase-locked loop providing a locked clock signal;

a controller coupled to the phase-locked loop, the controller receiving a status indication from the phase-locked loop, the controller encoding the status indication to provide a data encoding; and

a pulse-width modulator receiving the locked clock signal from the phase-locked loop and the data encoding from the controller, the pulse-width modulation determining duty times based on the data encoding,

wherein the controller further receives GPIO data and the data encoding further includes the GPIO data.

6. A network system, comprising:

a plurality of line cards, the plurality of line cards each providing a pulse-width modulated clock signal that includes encoded data; and

a timing card that receives the pulse-width modulated clock signals from each of the plurality of line cards, the timing card providing a clock signal from the pulse-width modulated clock signal from a selected one of the plurality of line cards,

wherein the timing card can switch from a first line card of the plurality of line cards to a second line card of the plurality of line cards based on data encoded in the pulse-width modulated clock signals,

wherein the timing card provides GPIO data from the data encoded in the pulse-width modulated clock signals.