Zero offset clock distribution
A method of distributing clock signals includes receiving a plurality of clock signals into a corresponding plurality of processing blocks; determining frequency offset data between a first clock signal of the plurality of clock signals and each of the other clock signals of the plurality of clock signals; periodically determining phase offset data between the first clock signal and the other clock signals; and transmitting the first clock signal, the frequency offset data, and the phase offset data on a pulse-width modulated clock signal. The method includes receiving a modulated clock signal, the modulated clock signal include a carrier clock signal, a frequency offset data, and a phase offset data on a pulse-width modulated clock signal; and recovering a plurality of clock signals based on the first clock signal, the frequency offset data, and the phase offset data.
1. A method of distributing clock signals, comprising
receiving a modulated clock signal, the modulated clock signal include a carrier clock signal, a frequency offset data, and a phase offset data on a pulse-width modulated clock signal; and
recovering a plurality of clock signals based on the first clock signal, the frequency offset data, and the phase offset data,
wherein recovering the plurality of clock signals comprises
receiving a communication indicating a time period for determining phase offset data;
determining receiver phase offset data over the time period;
comparing the receiver phase offset data with the phase offset data received on the pulse-width modulated clock signal to generate comparison phase offset data;
determining an adjustment to the frequency offset data based on the comparison phase offset data; and
determining each of the clock signals based on the adjustment and the frequency offset data for each of the clock signals.
2. The method of claim 1 , wherein the modulated clock signal is received in a first processing block, and further including:
in a second processing block, receiving a recovered carrier clock signal and frequency offset data corresponding to the second processing block from the first processing block, along with a frequency offset adjustment; and
recovering a clock signal corresponding to the second processing block from the recovered carrier clock signal, the frequency offset data, and the frequency offset adjustment.
3. A network transmitting device, comprising:
a plurality of processing blocks, each of the plurality of processing blocks receiving a corresponding plurality of clock signals,
wherein a first processing block of the plurality of processing blocks generates an output clock signal based on a first clock signal of the plurality of clock signals,
wherein each of the plurality of processing blocks except the first processing block compares a frequency of the first clock signal with a frequency of the corresponding one of the plurality of clock signals to generate frequency offset data,
wherein each of the plurality of processing blocks except the first processing block generates phase offset data comparing the corresponding one of the plurality of clock signals with the first clock signal over a specific time, and
wherein the first processing block encodes the frequency offset data and the phase offset data onto the output clock signal.
4. The network transmitting device of claim 3 , wherein each of the plurality of processing blocks includes a phase-locked loop.
5. The network transmitting device of claim 3 , wherein the first processing block encodes the frequency offset data and the phase offset data onto the output clock signal using pulse-width modulation.
6. A network receiving device, comprising:
a first processing block that receives an input signal from a network receiving device, the input signal including a first clock signal, encoded frequency offset data, and encoded phase offset data, wherein the first processing block recovers the first clock signal and retrieves the encoded frequency offset data and the encoded phase offset data; and
one or more second processing blocks coupled to the first processing block, the one or more second processing blocks receiving the first clock signal and the frequency offset data from the first processing block,
wherein the one or more second processing blocks generates a frequency offset adjustment based on a comparison of the phase offset data received with the input signal and receiver phase offset data generated in the one or more second processing blocks, and
wherein the one or more second processing blocks recover a corresponding clock signal from the first clock signal, the frequency offset data, and the frequency offset adjustment.
7. The network receiver device of claim 6 , wherein the first processing block includes a phase-locked loop.
8. The network receiver device of claim 6 , wherein the one or more second processing blocks include digitally controlled oscillators.
9. A network system, comprising:
a transmitting device, the transmitting device providing a modulated clock signal that includes a first clock signal, frequency offset data indicating the difference in frequency between the first clock signal and one or more second clock signals, and phase offset data indicating phase difference between the one or more second clock signals and the first clock signal over a specific time period; and
a receiving device, the receiving device receiving the modulated clock signal and recovering the frequency offset data and phase offset data, determining receiver phase offset data, comparing the receiver phase offset data and the phase offset data to generate an adjustment to the frequency offset data, and recovering the one or more second clock signals.