IP Library Granted Patent US 11,399,149
Granted Patent B2
US 11,399,149 · App. 16/522,580 · Granted Jul 26, 2022

Flexible latency-minimized delivery and management of disparate-rate data streams and sub-streams for processing

Inventors: James P. McFarland (Austin, TX); Nariankadu D. Hemkumar (Austin, TX); Sachin Deo (Austin, TX); Younes Djadi (Austin, TX)
Assignee: Cirrus Logic, Inc.
H04N5/378H04N5/3741H04N5/37455H04N19/132H04N19/146H04N19/184
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Quick Facts
Patent No.
US 11,399,149
App. No.
16/522,580
Granted
Jul 26, 2022
Kind
B2
Abstract

A system may include a processing engine and an analog-to-digital conversion interface subsystem communicatively coupled to the processing engine. The processing engine may be configured to process feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate and based on processing of the feedback data, generate digital control signals for controlling a system under control. The analog-to-digital conversion interface subsystem may be configured to flexibly control the processing of the processing engine and the generation of digital control signals by the processing engine to minimize latency in the generation of the digital control signals due to processing of the processing engine.

Claims (36)

1. A system comprising:

a processing engine configured to:

process feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate, and wherein the sample rate establishes an input sample rate of the plurality of data stream sequences and an output sample rate of digital control signals; and

based on processing of the feedback data, generate the digital control signals for controlling a system under control; and

an analog-to-digital conversion interface subsystem communicatively coupled to the processing engine and configured to control the processing of the processing engine and the generation of the digital control signals by the processing engine to reduce latency in the generation of the digital control signals due to processing of the processing engine, wherein the analog-to-digital conversion interface subsystem is further configured to modify the output sample rate from an initial output sample rate to a modified output sample rate, wherein the modified output sample rate is operable to align the digital control signals.

2. The system of claim 1 , wherein the analog-to-digital conversion interface subsystem includes a configuration subsystem to:

determine a number of slots in each of the plurality of data stream sequences; and

assign individual data channels of the analog feedback data to respective slots.

3. The system of claim 2 , wherein the configuration subsystem is further configured to assign at least one individual data channel to a plurality of respective slots.

4. The system of claim 1 , wherein a processing deadline for processing the plurality of data stream sequences is independent of the sample rate.

5. The system of claim 1 , wherein the system under control is a motor associated with a camera.

6. The system of claim 5 , wherein the feedback data is sensor data associated with the motor.

7. A method comprising:

processing feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate, and wherein the sample rate establishes an input sample rate of the plurality of data stream sequences and an output sample rate of digital control signals;

based on processing of the feedback data, generating the digital control signals for controlling a system under control;

controlling the processing of the processing engine and the generation of the digital control signals by the processing engine to reduce latency in the generation of the digital control signals due to processing of the processing engine; and

modifying the output sample rate from an initial output sample rate to a modified output sample rate, wherein the modified output sample rate is operable to align the digital control signals.

8. The method of claim 7 , further comprising:

determining a number of slots in each of the plurality of data stream sequences; and

assigning individual data channels of the analog feedback data to respective slots.

9. The method of claim 8 , further comprising assigning at least one individual data channel to a plurality of respective slots.

10. The method of claim 7 , wherein a processing deadline for processing the plurality of data stream sequences is independent of the sample rate.

11. The method of claim 7 , wherein the system under control is a motor associated with a camera.

12. The method of claim 11 , wherein the feedback data is sensor data associated with the motor.

13. A computer program product comprising a non-transitory computer usable medium having computer readable code physically embodied therein, said computer program product further comprising computer readable program code for:

processing feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate, and wherein the sample rate establishes an input sample rate of the plurality of data stream sequences and an output sample rate of digital control signals;

based on processing of the feedback data, generating the digital control signals for controlling a system under control;

controlling the processing of the processing engine and the generation of the digital control signals by the processing engine to reduce latency in the generation of the digital control signals due to processing of the processing engine; and

modifying the output sample rate from an initial output sample rate to a modified output sample rate, wherein the modified output sample rate is operable to align the digital control signals.

14. The computer program product of claim 13 , the computer readable program code further for:

determining a number of slots in each of the plurality of data stream sequences; and

assigning individual data channels of the analog feedback data to respective slots.

15. The computer program product of claim 14 , the computer readable program code further for assigning at least one individual data channel to a plurality of respective slots.

16. The computer program product of claim 13 , wherein a processing deadline for processing the plurality of data stream sequences is independent of the sample rate.

17. The computer program product of claim 13 , wherein the system under control is a motor associated with a camera.

18. The computer program product of claim 17 , wherein the feedback data is sensor data associated with the motor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2022
From: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
To: CIRRUS LOGIC, INC.
Reel/Frame 059427/0906 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2019
From: MCFARLAND, JAMES P.; HEMKUMAR, NARIANKADU D.; DEO, SACHIN; DJADI, YOUNES
To: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
Reel/Frame 050734/0953 →
Continuity (1)
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