IP Library Granted Patent US 11,073,951
Granted Patent B2
US 11,073,951 · App. 16/523,149 · Granted Jul 27, 2021

Method and device for improved accuracy of proximity and touch detection in mobile devices

Inventors: Chaouki Rouaissia (Neuchatel, CH); Jerald G. Ott, III (Escondido, CA)
Assignee: Semtech Corporation
G06F3/0443G06F3/04182H03K17/955H04M1/0266G06F2203/04101G06F2203/04103G06F2203/04107G06F2203/04108H03K2217/94015H03K2217/94031H03K2217/960705
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Quick Facts
Patent No.
US 11,073,951
App. No.
16/523,149
Granted
Jul 27, 2021
Kind
B2
Abstract

A mobile device has a proximity sensor. A compensation value of the proximity sensor is determined. The compensation value is compared to a reference compensation value to determine validity of the compensation value. A capacitance of the proximity sensor is measured. A value of the capacitance of the proximity sensor is adjusted based on the compensation value. A coefficient defining a relationship between a capacitance of the proximity sensor and a temperature of the mobile device is calculated. A temperature sensor is coupled to the proximity sensor. The temperature of the mobile device is measured. A value of the capacitance of the proximity sensor is adjusted based on the coefficient and the temperature of the mobile device. The adjusted capacitance value is compared to a threshold capacitance value to determine proximity of an object to the mobile device. A radio frequency signal is adjusted by detecting proximity.

Claims (47)

1. A capacitive sensing controller, comprising:

a first capacitive sensor input to provide a first sensor reading;

a second capacitive sensor input to provide a second sensor reading, wherein the second sensor reading is modified by a coefficient defining a relationship between the first capacitive sensor input and second capacitive sensor input;

an analog-to-digital converter (ADC) including an input of the ADC coupled to the first capacitive sensor input to receive the first sensor reading;

a digital register;

a digital processor coupled to read and write the first sensor reading of the first capacitive sensor input from an output of the ADC to the digital register, wherein the digital processor includes a control unit and arithmetic logic unit allowing the digital processor to execute instructions; and

a digital memory including a program executable by the digital processor stored in the digital memory, wherein the program is configured to cause the digital processor to read a value from the digital register and perform calculations using the value.

2. The capacitive sensing controller of claim 1 , wherein the program is configured to cause the digital processor to adjust the first sensor reading of the first capacitive sensor input based on the second reading of the second capacitive sensor input.

3. The capacitive sensing controller of claim 1 , further including an offset register that is writable by the digital processor or CPU.

4. The capacitive sensing controller of claim 1 , wherein the second capacitive sensor input is coupled to the input of the analog-to-digital converter.

5. The capacitive sensing controller of claim 4 , wherein the capacitive sensing controller is configured to time multiplex readings of the first capacitive sensor input and second capacitive sensor input through the analog-to-digital converter.

6. The capacitive sensing controller of claim 1 , further including a temperature sensor coupled to the second capacitive sensor input.

7. A capacitive sensing controller integrated circuit, comprising:

a first capacitive sensor input to provide a first sensor reading;

a second capacitive sensor input to provide a second sensor reading, wherein the second sensor reading is modified by a coefficient selected based on a range of values for the second sensor reading;

a digital processor coupled to the first capacitive sensor input, wherein the digital processor is configured to execute instructions;

a digital register configured to store the first sensor reading of the first capacitive sensor input, wherein the digital processor is coupled to read the digital register; and

a digital memory including a program executable by the digital processor stored in the digital memory, wherein the program is configured to cause the digital processor to read a value from the digital register and perform calculations using the value.

8. The capacitive sensing controller integrated circuit of claim 7 , further including an interrupt bit configured to be set or cleared based on a value of the digital register.

9. The capacitive sensing controller integrated circuit of claim 7 , further including an offset register coupled to the digital processor.

10. The capacitive sensing controller integrated circuit of claim 7 , further including a threshold register coupled to the digital processor.

11. The capacitive sensing controller integrated circuit of claim 7 , further including a temperature sensor coupled to the second capacitive sensor input, wherein the program is configured to cause the digital processor to modify the first sensor reading of the first capacitive sensor input based on a reading of the temperature sensor.

12. A capacitive sensing controller integrated circuit, comprising:

a first capacitive sensor input to provide a first sensor reading;

a second capacitive sensor input to provide a second sensor reading, wherein the second sensor reading is modified by a coefficient for the second capacitive sensor input;

a digital register configured to store the first sensor reading of the first capacitive sensor input; and

a digital processing unit coupled to the digital register, wherein the digital processing unit is programmable to read a value from the digital register and perform arbitrary digital processing using the value.

13. The capacitive sensing controller integrated circuit of claim 12 , wherein the digital processing unit is programmed to modify the first sensor reading of the first capacitive sensor input based on the second sensor reading of the second capacitive sensor input.

14. The capacitive sensing controller integrated circuit of claim 12 , further including an offset compensation block coupled between the first capacitive sensor input and the digital processing unit.

15. A method of making a capacitive sensing controller, comprising:

providing an integrated circuit including a digital processor and a first capacitive sensor input to provide a first sensor reading to the digital processor and a second sensor capacitive input to provide a second sensor reading, wherein the second sensor reading is modified by a coefficient; and

programming the digital processor to read the first sensor reading of the first sensor capacitive input from a digital register and process the first sensor reading.

16. The method of claim 15 , further including programming the digital processor to modify the first sensor reading of the first capacitive sensor input based on the second sensor reading of the second capacitive sensor input of the integrated circuit.

17. The method of claim 16 , further including programming the digital processor to multiply the second sensor reading of the second capacitive sensor input by the coefficient prior to modifying the first sensor reading of the first capacitive sensor input.

18. The method of claim 15 , further including providing a CPU coupled to the digital processor.

19. The method of claim 15 , further including programming the digital processor to adjust the first sensor reading of the first capacitive sensor input based on a detected temperature.

20. The method of claim 19 , further including reading the detected temperature by measuring a self-capacitance via the second capacitive sensor input of the integrated circuit.

21. A capacitive sensing controller, comprising:

a first capacitive sensor input to provide a first sensor reading;

a second capacitive sensor input to provide a second sensor reading, wherein the second sensor reading is modified by a coefficient;

a digital processing unit coupled to the first capacitive sensor input;

a digital register configured to store the first sensor reading of the first capacitive sensor input; and

a CPU configured to process the first sensor reading of the first capacitive sensor input.

22. The capacitive sensing controller of claim 21 , wherein the digital processing unit is programmed to adjust the first sensor reading of the first capacitive sensor input based on the second sensor reading of the second capacitive sensor input.

23. The capacitive sensing controller of claim 22 , further including a temperature sensor coupled to the second capacitive sensor input.

24. The capacitive sensing controller of claim 23 , wherein the capacitive sensing controller is configured to time multiplex readings of the first capacitive sensor input and second capacitive sensor input through the analog-to-digital converter.

25. The capacitive sensing controller of claim 22 , further including an analog-to-digital converter, wherein the first capacitive sensor input and second capacitive sensor input are coupled to the digital processing unit through the analog-to-digital converter.

Assignments (3)
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (050437/0902) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062784/0069 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: ROUAISSIA, CHAOUKI; OTT, JERALD G., III
To: SEMTECH CORPORATION
Reel/Frame 052288/0538 →
SECURITY INTEREST Recorded Sep 19, 2019
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 050437/0902 →
Continuity (4)
Continuation 16388668 · Apr 18, 2019
Continuation 15402642 · Jan 10, 2017
Continuation 14530112 · Oct 31, 2014
Related Publication 20190346964A1 · Nov 14, 2019