IP Library Granted Patent US 11,385,941
Granted Patent B2
US 11,385,941 · App. 16/527,500 · Granted Jul 12, 2022

System and method for address space slicing with strong CPU core affinity

Inventors: Ronen Gazit (Tel Aviv, IL); Vladimir Shveidel (Pardes-Hana, IL)
Assignee: EMC IP HOLDING COMPANY, LLC
G06F9/5077G06F2209/5011
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Quick Facts
Patent No.
US 11,385,941
App. No.
16/527,500
Granted
Jul 12, 2022
Kind
B2
Abstract

A method, computer program product, and computer system for partitioning, by a computing device, resources between a plurality of central processing unit (CPU) cores. A logical block address (LBA) space of a user may be divided into a slice with an affinity to a CPU core of the plurality of CPU cores. IO flow processing may be processed by the CPU core of the plurality of CPU cores associated with the LBA space divided into the slice.

Claims (26)

1. A computer-implemented method comprising:

partitioning, by a computing device, resources between a plurality of central processing unit (CPU) cores;

dividing a logical block address (LBA) space of a user into a plurality of slices, wherein each slice of the plurality of slices has an affinity to a respective CPU core of the plurality of CPU cores, wherein dividing the LBA space into the plurality of slices includes providing even slice distribution between the plurality of CPU cores, wherein dividing includes ignoring a pre-determined number of bits of at least one LBA address of the LBA addresses of the LBA address space; and

processing IO flow processing by the respective CPU core of the plurality of CPU cores associated with the LBA space divided into the plurality of slices, wherein the resources between the plurality of CPU cores are a function of the LBA space such that when the IO flow processing is processed by the respective CPU core associated with the LBA space, access to the resources between the plurality of CPU cores are processed only from the same respective CPU core associated with the LBA space.

2. The computer-implemented method of claim 1 wherein the resources include physical resources and objects.

3. The computer-implemented method of claim 2 wherein the physical resources and objects include at least one of memory pools, data pages, and metadata pages.

4. The computer-implemented method of claim 1 wherein the resources include logical entities.

5. The computer-implemented method of claim 4 wherein the logical entities include a logical unit number (LUN) address.

6. The computer-implemented method of claim 1 wherein LBA addresses of the LBA address space involved in a same processing IO flow of the IO flow processing relate to the plurality of slices, and wherein the LBA addresses of the LBA address space involved in the same processing IO flow relate to the plurality of slices when the LBA addresses of the LBA address space are related to a same leaf.

7. A computer program product residing on a non-transitory computer readable storage medium having a plurality of instructions stored thereon which, when executed across one or more processors, causes at least a portion of the one or more processors to perform operations comprising:

partitioning resources between a plurality of central processing unit (CPU) cores;

dividing a logical block address (LBA) space of a user into a plurality of slices, wherein each slice of the plurality of slices has an affinity to a respective CPU core of the plurality of CPU cores, wherein dividing the LBA space into the plurality of slices includes providing even slice distribution between the plurality of CPU cores, wherein dividing includes ignoring a pre-determined number of bits of at least one LBA address of the LBA addresses of the LBA address space; and

processing IO flow processing by the respective CPU core of the plurality of CPU cores associated with the LBA space divided into the plurality of slices, wherein the resources between the plurality of CPU cores are a function of the LBA space such that when the IO flow processing is processed by the respective CPU core associated with the LBA space, access to the resources between the plurality of CPU cores are processed only from the same respective CPU core associated with the LBA space.

8. The computer program product of claim 7 wherein the resources include physical resources and objects.

9. The computer program product of claim 8 wherein the physical resources and objects include at least one of memory pools, data pages, and metadata pages.

10. The computer program product of claim 7 wherein the resources include logical entities.

11. The computer program product of claim 10 wherein the logical entities include a logical unit number (LUN) address.

12. The computer program product of claim 7 wherein LBA addresses of the LBA address space involved in a same processing IO flow of the IO flow processing relate to the plurality of slices, and wherein the LBA addresses of the LBA address space involved in the same processing IO flow relate to the plurality of slices when the LBA addresses of the LBA address space are related to a same leaf.

13. A computing system including one or more processors and one or more memories configured to perform operations comprising:

partitioning resources between a plurality of central processing unit (CPU) cores;

dividing a logical block address (LBA) space of a user into a plurality of slices, wherein each slice of the plurality of slices has an affinity to a respective CPU core of the plurality of CPU cores, wherein dividing the LBA space into the plurality of slices includes providing even slice distribution between the plurality of CPU cores, wherein dividing includes ignoring a pre-determined number of bits of at least one LBA address of the LBA addresses of the LBA address space; and

processing IO flow processing by the respective CPU core of the plurality of CPU cores associated with the LBA space divided into the plurality of slices, wherein the resources between the plurality of CPU cores are a function of the LBA space such that when the IO flow processing is processed by the respective CPU core associated with the LBA space, access to the resources between the plurality of CPU cores are processed only from the same respective CPU core associated with the LBA space.

14. The computing system of claim 13 wherein the resources include physical resources and objects.

15. The computing system of claim 14 wherein the physical resources and objects include at least one of memory pools, data pages, and metadata pages.

16. The computing system of claim 13 wherein the resources include logical entities, and wherein the logical entities include a logical unit number (LUN) address.

17. The computing system of claim 13 wherein LBA addresses of the LBA address space involved in a same processing IO flow of the IO flow processing relate to the plurality of slices, and wherein the LBA addresses of the LBA address space involved in the same processing IO flow relate to the plurality of slices when the LBA addresses of the LBA address space are related to a same leaf.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (050724/0571) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0088 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST AT REEL 050406 FRAME 421 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058213/0825 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Oct 15, 2019
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 050724/0571 →
SECURITY AGREEMENT Recorded Sep 17, 2019
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 050406/0421 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2019
From: GAZIT, RONEN; SHVEIDEL, VLADIMIR
To: EMC IP HOLDING COMPANY, LLC
Reel/Frame 049917/0171 →
Continuity (1)
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