Peak suppression circuit, peak suppression method, and transmitter
A peak suppression circuit includes a memory, and a processor coupled to the memory and the processor configured to suppress a first peak of a transmission signal according to a first sampling signal having a predetermined period, delay the transmission signal where the first peak is suppressed by a predetermined time corresponding to a period shorter than the predetermined period, and suppress a second peak of the delayed transmission signal according to a second sampling signal having the predetermined period.
1. A peak suppression circuit comprising:
a memory; and
a processor coupled to the memory and the processor configured to:
suppress a first peak of a transmission signal according to a first sampling signal having a predetermined period;
delay the transmission signal where the first peak is suppressed by a predetermined time that corresponds to a period shorter than the predetermined period of the first sampling signal; and
suppress a second peak of the delayed transmission signal according to a second sampling signal having the predetermined period.
2. The peak suppression circuit according to claim 1 ,
wherein the processor is further configured to:
detect timings of the first peak and the second peak which exceed predetermined threshold levels, respectively, among peaks of the transmission signal;
generate suppression signals having peaks in synchronization with the detected timings, respectively; and
synthesize the delayed transmission signal with the suppression signals, respectively.
3. The peak suppression circuit according to claim 1 ,
wherein the processor is configured to:
suppress an (n−1)-th peak of the transmission signal according to an (n−1)-th sampling signal having the predetermined period,
delay the transmission signal where the (n−1)-th peak is suppressed by the predetermined time that corresponds to a period shorter than the predetermined period, and
suppress an n-th peak of the delayed transmission signal according to an n-th sampling signal having the predetermined period,
wherein the n is an integer of 2 or more.
4. The peak suppression circuit according to claim 3 ,
wherein the predetermined time is a time having 1/n of a length of the predetermined period.
5. A peak suppression method comprising:
suppressing a first peak of a transmission signal according to a first sampling signal having a predetermined period;
delaying the transmission signal where the first peak is suppressed by a predetermined time that corresponds to a period shorter than the predetermined period of the first sampling signal; and
suppressing a second peak of the delayed transmission signal according to a second sampling signal having the predetermined period, by a processor.
6. A transmitter comprising:
a memory;
a processor coupled to the memory and the processor configured to:
suppress a first peak of a transmission signal according to a first sampling signal having a predetermined period;
delay the transmission signal where the first peak is suppressed by a predetermined time that corresponds to a period shorter than the predetermined period; and
suppress a second peak of the delayed transmission signal according to a second sampling signal having the predetermined period of the first sampling signal;
an amplifier configured to amplify the transmission signal where the second peak is suppressed; and
an antenna configured to transmit the transmission signal amplified by the amplifier.