Semiconductor memory device, memory system, and write method

1. A memory system comprising:

a semiconductor memory device having a memory cell array including a memory cell capable of holding at least 4-bit data; and

a controller configured to control a first write operation and a second write operation based on the 4-bit data in the semiconductor memory device,

wherein the controller includes a conversion circuit configured to convert the 4-bit data into 2-bit data,

the semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation,

the first write operation is executed based on the 4-bit data received from the controller, and

the second write operation is executed based on the 4-bit data recovered by the recovery controller.

2. The system according to claim 1 , wherein

when the controller gives an instruction on execution of the second write operation, the semiconductor memory device sequentially executes read operation of the memory cell, recovery operation of the 4-bit data, and the second write operation.

3. The system according to claim 1 , wherein

a threshold voltage of the memory cell is included in any one of a plurality of threshold distributions corresponding to the 4-bit data, and

assignment of the 2-bit data to the plurality of threshold distributions is different by 1 bit between the threshold distributions adjacent to each other.

4. A writing method comprising:

executing a first write operation of writing 4-bit data in a memory cell,

converting the 4-bit data into 2-bit data;

reading data written by the first write operation from the memory cell;

recovering the 4-bit data based on the 2-bit data and the data read from the memory cell; and

executing a second write operation for the memory cell based on the recovered 4-bit data.