IP Library Granted Patent US 11,379,387
Granted Patent B2
US 11,379,387 · App. 16/529,900 · Granted Jul 5, 2022

Storage system with submission queue selection utilizing application and submission queue priority

Inventors: Kurumurthy Gokam (Bangalore, IN); Venkatesh Doddamane Nagaraj (Bangalore, IN)
Assignee: EMC IP Holding Company LLC
G06F13/1642G06F3/067G06F3/0607G06F3/0631G06F3/0679
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Quick Facts
Patent No.
US 11,379,387
App. No.
16/529,900
Granted
Jul 5, 2022
Kind
B2
Abstract

A host device comprises a plurality of communication adapters and is configured to communicate with a storage system. Each communication adapter comprises a plurality of input-output (IO) submission queues each having a submission queue priority class. A multi-path input-output (MPIO) driver is configured to deliver IO operations to the storage system over the network. The MPIO driver obtains an IO operation that targets a given logical volume of the storage system and determines a process tag value associated with the obtained IO operation. A mapping between the determined process tag value and a given submission queue priority class is determined and IO submission queues are identified as having the given submission queue priority class based at least in part on the mapping. A target IO submission queue is selected from the identified IO submission queues and the IO operation is dispatched to the selected target IO submission queue.

Claims (67)

1. An apparatus comprising:

a host device configured to communicate over a network with a storage system comprising a plurality of storage devices;

the host device comprising:

at least one processing device and a plurality of communication adapters, each communication adapter comprising a plurality of input-output submission queues, each of the input-output submission queues having a submission queue priority class; and

a multi-path input-output driver configured to deliver input-output operations from the host device to the storage system over the network;

wherein the multi-path input-output driver is further configured:

to obtain an input-output operation that targets a given logical volume of the storage system;

to determine a process tag value associated with the obtained input-output operation;

to determine a mapping between the determined process tag value and a given submission queue priority class;

to identify one or more of the input-output submission queues as having the given submission queue priority class based at least in part on the mapping;

to select a target input-output submission queue from the identified one or more input-output submission queues; and

to dispatch the obtained input-output operation to the selected target input-output submission queue.

2. The apparatus of claim 1 wherein determining the mapping between the determined process tag value and the given submission queue priority class comprises obtaining at least one priority mapping data structure and accessing an entry in the obtained at least one priority mapping data structure that corresponds to the determined process tag value to map the determined process tag value to the given submission queue priority class.

3. The apparatus of claim 2 wherein the at least one priority mapping data structure comprises a first priority mapping data structure and a second priority mapping data structure;

wherein the first priority mapping data structure comprises a first plurality of entries, each entry of the first plurality of entries corresponding to one of a plurality of process tag values, the plurality of process tag values comprising the determined process tag value;

wherein the entry of the first plurality of entries that corresponds to the determined process tag value maps the determined process tag value to a corresponding application priority level; and

wherein the second priority mapping data structure comprises a second plurality of entries, a given entry of the second plurality of entries comprising the corresponding application priority level, the given entry mapping the corresponding application priority level to the given submission queue priority class.

4. The apparatus of claim 3 wherein the entry of the first plurality of entries that corresponds to the determined process tag value comprises a storage system priority class;

wherein the storage system priority class defines a correspondence between the process tag value and the application priority level; and

wherein the mapping of the determined process tag value to the corresponding application priority level is based at least in part on the correspondence defined by the storage system priority class.

5. The apparatus of claim 3 wherein the given entry of the second plurality of entries further comprises an indication of which input-output submission queues of the plurality of input-output submission queues have the given submission queue priority class; and

wherein identifying the one or more of the input-output submission queues as having the given submission queue priority class based at least in part on the mapping comprises identifying the one or more of the input-output submission queues based at least in part on the given entry of the second plurality of entries of the second priority mapping data structure.

6. The apparatus of claim 2 wherein the at least one priority mapping data structure comprises a plurality of entries, each entry of the plurality of entries corresponding to one of a plurality of process tag values, the plurality of process tag values comprising the determined process tag value; and

wherein a given entry of the plurality of entries that corresponds to the determined process tag value maps the determined process tag value to the given submission queue priority class.

7. The apparatus of claim 6 wherein the given entry of the plurality of entries further comprises an indication of which input-output submission queues of the plurality of input-output submission queues have the given submission queue priority class; and

wherein identifying the one or more of the input-output submission queues as having the given submission queue priority class based at least in part on the mapping comprises identifying the one or more of the input-output submission queues based at least in part on the given entry of the plurality of entries of the at least one priority mapping data structure.

8. The apparatus of claim 1 wherein the plurality of input-output submission queues comprise non-volatile memory express (NVMe) input-output submission queues.

9. A method comprising:

obtaining, by a multi-path input-output driver of a host device configured to communicate over a network with a storage system comprising a plurality of storage devices, an input-output operation that targets a given logical volume of the storage system, the host device comprising at least one processing device and a plurality of communication adapters, each communication adapter comprising a plurality of input-output submission queues, each of the input-output submission queues having a submission queue priority class;

determining, by the multi-path input-output driver, a process tag value associated with the obtained input-output operation;

determining, by the multi-path input-output driver, a mapping between the determined process tag value and a given submission queue priority class;

identifying, by the multi-path input-output driver, one or more of the input-output submission queues as having the given submission queue priority class based at least in part on the mapping;

selecting, by the multi-path input-output driver, a target input-output submission queue from the identified one or more input-output submission queues; and

dispatching, by the multi-path input-output driver, the obtained input-output operation to the selected target input-output submission queue.

10. The method of claim 9 wherein determining the mapping between the determined process tag value and the given submission queue priority class comprises obtaining at least one priority mapping data structure and accessing an entry in the obtained at least one priority mapping data structure that corresponds to the determined process tag value to map the determined process tag value to the given submission queue priority class.

11. The method of claim 10 wherein the at least one priority mapping data structure comprises a first priority mapping data structure and a second priority mapping data structure;

wherein the first priority mapping data structure comprises a first plurality of entries, each entry of the first plurality of entries corresponding to one of a plurality of process tag values, the plurality of process tag values comprising the determined process tag value;

wherein the entry of the first plurality of entries that corresponds to the determined process tag value maps the determined process tag value to a corresponding application priority level; and

wherein the second priority mapping data structure comprises a second plurality of entries, a given entry of the second plurality of entries comprising the corresponding application priority level, the given entry mapping the corresponding application priority level to the given submission queue priority class.

12. The method of claim 11 wherein the entry of the first plurality of entries that corresponds to the determined process tag value comprises a storage system priority class;

wherein the storage system priority class defines a correspondence between the process tag value and the application priority level; and

wherein the mapping of the determined process tag value to the corresponding application priority level is based at least in part on the correspondence defined by the storage system priority class.

13. The method of claim 11 wherein the given entry of the second plurality of entries further comprises an indication of which input-output submission queues of the plurality of input-output submission queues have the given submission queue priority class; and

wherein identifying the one or more of the input-output submission queues as having the given submission queue priority class based at least in part on the mapping comprises identifying the one or more of the input-output submission queues based at least in part on the given entry of the second plurality of entries of the second priority mapping data structure.

14. The method of claim 10 wherein the at least one priority mapping data structure comprises a plurality of entries, each entry of the plurality of entries corresponding to one of a plurality of process tag values, the plurality of process tag values comprising the determined process tag value; and

wherein a given entry of the plurality of entries that corresponds to the determined process tag value maps the determined process tag value to the given submission queue priority class.

15. The method of claim 14 wherein the given entry of the plurality of entries further comprises an indication of which input-output submission queues of the plurality of input-output submission queues have the given submission queue priority class; and

wherein identifying the one or more of the input-output submission queues as having the given submission queue priority class based at least in part on the mapping comprises identifying the one or more of the input-output submission queues based at least in part on the given entry of the plurality of entries of the at least one priority mapping data structure.

16. The method of claim 9 wherein the plurality of input-output submission queues comprise non-volatile memory express (NVMe) input-output submission queues.

17. A computer program product comprising a non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code, when executed by a host device that is configured to communicate over a network with a storage system comprising a plurality of storage devices, the host device comprising at least one processing device and a plurality of communication adapters, each communication adapter comprising a plurality of input-output submission queues, each of the input-output submission queues having a submission queue priority class, the host device further comprising a multi-path input-output driver configured to deliver input-output operations from the host device to the storage system over the network, causes the multi-path input-output driver:

to obtain an input-output operation that targets a given logical volume of the storage system;

to determine a process tag value associated with the obtained input-output operation;

to determine a mapping between the determined process tag value and a given submission queue priority class;

to identify one or more of the input-output submission queues as having the given submission queue priority class based at least in part on the mapping;

to select a target input-output submission queue from the identified one or more input-output submission queues; and

to dispatch the obtained input-output operation to the selected target input-output submission queue.

18. The computer program product of claim 17 wherein determining the mapping between the determined process tag value and the given submission queue priority class comprises obtaining at least one priority mapping data structure and accessing an entry in the obtained at least one priority mapping data structure that corresponds to the determined process tag value to map the determined process tag value to the given submission queue priority class.

19. The computer program product of claim 18 wherein the at least one priority mapping data structure comprises a first priority mapping data structure and a second priority mapping data structure;

wherein the first priority mapping data structure comprises a first plurality of entries, each entry of the first plurality of entries corresponding to one of a plurality of process tag values, the plurality of process tag values comprising the determined process tag value;

wherein the entry of the first plurality of entries that corresponds to the determined process tag value maps the determined process tag value to a corresponding application priority level;

wherein the second priority mapping data structure comprises a second plurality of entries, a given entry of the second plurality of entries comprising the corresponding application priority level, the given entry mapping the corresponding application priority level to the given submission queue priority class;

wherein the given entry of the second plurality of entries further comprises an indication of which input-output submission queues of the plurality of input-output submission queues have the given submission queue priority class; and

wherein identifying the one or more of the input-output submission queues as having the given submission queue priority class based at least in part on the mapping comprises identifying the one or more of the input-output submission queues based at least in part on the given entry of the second plurality of entries of the second priority mapping data structure.

20. The computer program product of claim 18 wherein the at least one priority mapping data structure comprises a plurality of entries, each entry of the plurality of entries corresponding to one of a plurality of process tag values, the plurality of process tag values comprising the determined process tag value;

wherein a given entry of the plurality of entries that corresponds to the determined process tag value maps the determined process tag value to the given submission queue priority class;

wherein the given entry of the plurality of entries further comprises an indication of which input-output submission queues of the plurality of input-output submission queues have the given submission queue priority class; and

wherein identifying the one or more of the input-output submission queues as having the given submission queue priority class based at least in part on the mapping comprises identifying the one or more of the input-output submission queues based at least in part on the given entry of the plurality of entries of the at least one priority mapping data structure.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (050724/0571) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0088 →
RELEASE OF SECURITY INTEREST AT REEL 050406 FRAME 421 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058213/0825 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Oct 15, 2019
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 050724/0571 →
SECURITY AGREEMENT Recorded Sep 17, 2019
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 050406/0421 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2019
From: GOKAM, KURUMURTHY; NAGARAJ, VENKATESH DODDAMANE
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 049939/0306 →