Methods for row hammer mitigation and memory devices and systems employing the same
A method of operating a memory device is provided, comprising determining a number of operations corresponding to a memory location during a first timing period; and scheduling an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold. A memory device is provided, comprising a memory including a memory location; and circuitry configured to: determine a number of operations corresponding to the memory location during a first timing period; and schedule an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold.
1. A method of operating a memory device, comprising:
periodically refreshing the memory device with refresh operations at an integer multiple of a base refresh period;
determining a number of operations corresponding to a memory location during a first base refresh period; and
scheduling an extra non-periodic refresh operation for the memory location after the first base refresh period when the determined number of operations exceeds a predetermined threshold.
2. The method of claim 1 , wherein the extra non-periodic refresh operation is scheduled at the completion of the first base refresh period if another refresh operation is not already scheduled at the completion of the first base refresh period.
3. The method of claim 1 , wherein the extra non-periodic refresh operation is scheduled at the completion of a second base refresh period immediately following the first base refresh period if another refresh operation is already scheduled at the completion of the first base refresh period.
4. The method of claim 1 , further comprising:
maintaining a count of refresh operations scheduled for the memory location.
5. The method of claim 4 , wherein maintaining the count comprises determining repeated refresh commands to the same memory location without a corresponding increase in a refresh address counter.
6. The method of claim 1 , wherein the operations comprise activations.
7. The method of claim 1 , wherein the memory location comprises a memory bank.
8. The method of claim 1 , wherein the memory location comprises a sub-bank region of a memory bank.
9. The method of claim 1 , wherein the memory device comprises a dynamic random access memory (DRAM) device.
10. The method of claim 1 , wherein the scheduling the extra non-periodic refresh operation is dependent upon the integer multiple of the memory device being below a predetermined threshold value.
11. A memory device, comprising:
a memory including a memory location; and
circuitry configured to:
periodically refresh the memory device with refresh operations at an integer multiple of a base refresh period;
determine a number of operations corresponding to the memory location during a first base refresh period; and
schedule an extra non-periodic refresh operation for the memory location after the first base refresh period when the determined number of operations exceeds a predetermined threshold.
12. The memory device of claim 11 , wherein the circuitry is configured to schedule the extra non-periodic refresh operation at the completion of the first base refresh period if another refresh operation is not already scheduled at the completion of the first base refresh period.
13. The memory device of claim 11 , wherein the circuitry is configured to schedule the extra non-periodic refresh operation at the completion of a second base refresh period immediately following the first base refresh period if another refresh operation is already scheduled at the completion of the first base refresh period.
14. The memory device of claim 11 , wherein the circuitry is further configured to maintain a count of extra non-periodic refresh operations scheduled for the memory location.
15. The memory device of claim 14 , wherein the circuitry is configured to maintain the count by determining repeated refresh commands to the same memory location without a corresponding increase in a refresh address counter.
16. The memory device of claim 11 , wherein the operations comprise activations.
17. The memory device of claim 11 , wherein the memory location comprises a memory bank.
18. The memory device of claim 11 , wherein the memory location comprises a sub-bank region of a memory bank.
19. The memory device of claim 11 , wherein the memory device comprises a dynamic random access memory (DRAM) device.
20. The memory device of claim 11 , wherein the circuitry is further configured to maintain the determined number of operations in a counter of the memory device.
21. The memory device of claim 20 , wherein the circuitry is configured to reset the counter upon completion of the first base refresh period.
22. The memory device of claim 20 , wherein a memory module comprises the memory and wherein a host device or controller comprise the circuitry.
23. The memory device of claim 11 , wherein the circuitry is further configured to schedule the extra non-periodic refresh operation for the memory location in response to a determination that the integer multiple of the memory device is below a predetermined threshold value.