Automated verification code generation based on a hardware design and design data

1. A method comprising:

receiving, by a processing device, inputs from a user regarding a hardware design for a device under test (DUT);

presenting, by the processing device, cover group attribute suggestions to the user based on the hardware design;

receiving, by the processing device, cover group information from the user corresponding to one or more cover group attributes of one or more cover groups based on the cover group attribute suggestions; and

generating automatically, by the processing device, verification code, including one or more cover group definitions, based on the cover group information;

receiving, by the processing device, inputs from the user regarding a verification plan for the DUT; and

mapping, by the processing device, each of the one or more cover groups to items of the verification plan, wherein the items of the verification plan are mapped to a portion of the hardware design, and wherein the mapping links an item of the verification plan, one or more cover group, and the hardware design.

2. The method of claim 1 , further comprising:

receiving, by the processing device, inputs from the user regarding development/design data for the DUT.

3. The method of claim 2 , further comprising:

receiving, by the processing device, verification/testing results corresponding to the hardware design and the one or more cover groups; and

mapping, by the processing device, portions of the verification/testing results to separate cover groups in the one or more cover groups.

4. The method of claim 3 , further comprising:

presenting, by the processing device, verification/testing data, including the verification/testing results, to the user,

wherein the presentation indicates relationships between the verification/testing results, the one or more cover groups, the verification plan, and the development/design data.

5. The method of claim 1 , wherein the generation of the verification code is based on and in conformance with a specification for cover groups.

6. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

receive inputs from a user regarding a hardware design for a device under test (DUT);

present cover group attribute suggestions to the user based on the hardware design;

receive cover group information from the user corresponding to one or more cover group attributes of one or more cover groups based on the cover group attribute suggestions; and

generate verification code automatically, including one or more cover group definitions, based on the cover group information;

receive inputs from the user regarding a verification plan for the DUT; and

map each of the one or more cover groups to items of the verification plan, wherein the items of the verification plan are mapped to a portion of the hardware design.

7. The non-transitory computer-readable medium of claim 6 , wherein the processing device is further to:

receive inputs from the user regarding development/design data for the DUT.

8. The non-transitory computer-readable medium of claim 7 , wherein the processing device is further to:

receive verification/testing results corresponding to the hardware design and the one or more cover groups; and

map portions of the verification/testing results to separate cover groups in the one or more cover groups.

9. The non-transitory computer-readable medium of claim 8 , wherein the processing device is further to:

present verification/testing data, including the verification/testing results, to the user,

wherein the presentation indicates relationships between the verification/testing results, the one or more cover groups, the verification plan, and the development/design data.

10. The non-transitory computer-readable medium of claim 6 , wherein the generation of the verification code is based on and in conformance with a specification for cover groups.

11. A system comprising:

a plurality of memory components; and

a processing device, operatively coupled with the plurality of memory components, to:

receive inputs from a user regarding a hardware design for a device under test (DUT);

present cover group attribute suggestions to the user based on the hardware design;

receive cover group information from the user corresponding to one or more cover group attributes of one or more cover groups based on the cover group attribute suggestions; and

generate verification code automatically, including one or more cover group definitions, based on the cover group information

receive inputs from the user regarding a verification plan for the DUT; and

map each of the one or more cover groups to items of the verification plan, wherein the items of the verification plan are mapped to a portion of the hardware design.

12. The system of claim 1 , wherein the processing device is further to:

receive inputs from the user regarding development/design data for the DUT.

13. The system of claim 12 , wherein the processing device is further to:

receive verification/testing results corresponding to the hardware design and the one or more cover groups; and

map portions of the verification/testing results to separate cover groups in the one or more cover groups.

14. The system of claim 13 , wherein the processing device is further to:

present verification/testing data, including the verification/testing results, to the user,

wherein the presentation indicates relationships between the verification/testing results, the one or more cover groups, the verification plan, and the development/design data.

15. The system of claim 11 , wherein the generation of the verification code is based on and in conformance with a specification for cover groups.