IP Library Granted Patent US 10,840,869
Granted Patent B2
US 10,840,869 · App. 16/536,244 · Granted Nov 17, 2020

Capacitive MEMS microphone with active compression

Inventor: Hassan Ihs (San Diego, CA)
Assignee: Chaoyang Semiconductor Jiangyin Technology Co., Ltd.
H03G3/3005H03F3/183H03M1/12H03M3/30H04R1/04
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Quick Facts
Patent No.
US 10,840,869
App. No.
16/536,244
Granted
Nov 17, 2020
Kind
B2
Abstract

A digital microphone compresses a large voltage swing signal from a MEMS capacitor to a signal suitable for processing by integrated circuitry. The compression may be performed in an analog domain by selectively coupling adjustment capacitors in parallel to the MEMS capacitor. The digital microphone may decompress the signal in the digital domain using a decompression technique substantially an inverse of the compression performed in the analog domain.

Claims (18)

1. A digital microphone, comprising:

a microelectromechanical system (MEMS) capacitor;

a plurality of adjustment capacitors selectively coupleable in parallel to the MEMS capacitor, the adjustment capacitors selectively coupleable to the MEMS capacitor to achieve a compression in the form of x/(1+N|x|) of a voltage output of the MEMS capacitor, x being related to pressure applied to the MEMS capacitor, N being a compression index number greater than 1; and

a processing chain coupled to one side of the MEMS capacitor, the processing chain including, in sequence, a preamplifier, an analog-to-digital converter (ADC), and a decompression module, the decompression module being configured to perform a decompression substantially an inverse of the compression in the form of x/(1+N|x|).

2. The digital microphone of claim 1 , wherein the MEMS capacitor and adjustment capacitors are coupled to a bias voltage greater than a supply voltage coupled to the processing chain.

3. The digital microphone of claim 1 , wherein the decompression module is configured to perform the decompression in a digital domain.

4. The digital microphone of claim 1 , further comprising a gain error compensation block configured to adjust the compression index based on a ratio of capacitances of the MEMS capacitor and the adjustment capacitors.

5. The digital microphone of claim 1 , further comprising a digital filter in the processing chain between the ADC and the decompression module, the digital filter configured to suppress quantization noise generated by the ADC.

6. The digital microphone of claim 1 , wherein the ADC comprises a sigma delta ADC.

7. The digital microphone of claim 1 wherein the compression of the form x/(1+N|x|) comprises compression of the form x/(1+10x).

8. The digital microphone of claim 1 wherein the compression of the form x/(1+N|x|) comprises compression of the form x/(1+16x).

9. The digital microphone of claim 1 , wherein the decompression is a decompression in a form of v/(1−(N+1)|v|) for a positive voltage signal v and v/(1−(N−1)|v|) for a negative voltage signal v.

10. A method for processing signals for a digital microphone, comprising:

selectively coupling a plurality of adjustment capacitors in parallel with a microelectromechanical system (MEMS) capacitor serving as a sensor for a digital microphone, so as to perform a first compression technique on a signal generated by the MEMS capacitor;

amplifying the signal from the MEMS capacitor, to provide an amplified signal;

digitizing the amplified signal, to prove a digital signal; and

performing a digital operation on the digital signal, the digital operation being an inverse of the first compression technique, wherein the first compression technique is a compression in the form of x/(1+N|x|), x being related to pressure applied to the MEMS capacitor, N being a compression index number greater than 1.

11. The method of claim 10 , wherein the inverse of the first compression technique is a decompression in a form of v/(1−(N+1)|v|) for a positive voltage signal v and v/(1−(N−1)|v|) for a negative voltage signal v.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2023
From: CHAOYANG SEMICONDUCTOR (SHANGHAI) CO., LTD.
To: ENDURA IP HOLDINGS LTD.
Reel/Frame 063424/0226 →
CHANGE OF NAME Recorded Mar 29, 2022
From: CHAOYANG SEMICONDUCTOR JIANGYIN TECHNOLOGY CO., LTD.
To: CHAOYANG SEMICONDUCTOR (SHANGHAI) CO., LTD
Reel/Frame 061088/0212 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2020
From: IHS, HASSAN
To: ENDURA TECHNOLOGIES (INTERNATIONAL) LIMITED
Reel/Frame 053800/0853 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2020
From: ENDURA TECHNOLOGIES (INTERNATIONAL) LIMITED
To: CHAOYANG SEMICONDUCTOR JIANGYIN TECHNOLOGY CO., LTD.
Reel/Frame 053640/0558 →
Continuity (2)
Provisional Application 62715963 · Aug 8, 2018
Related Publication 20200052668A1 · Feb 13, 2020