Semiconductor memory device

1. A semiconductor memory device, comprising:

a first memory cell;

a first interconnect coupled to the first memory cell, the first interconnect extending in a first direction in a first interconnect layer, and having a first end surface crossing the first direction;

a first sense amplifier coupled to the first interconnect;

a second interconnect coupled to the first sense amplifier, the second interconnect extending in the first direction in the first interconnect layer, and having a second end surface crossing the first direction; and

a first latch circuit coupled to the second interconnect,

wherein the first end surface is opposed to the second end surface.

2. The device of claim 1 , further comprising:

a third interconnect in a second interconnect layer, the second interconnect layer being at a position different from the first interconnect layer when viewed in a stacking direction,

wherein the first sense amplifier and the second interconnect being are coupled via the third interconnect.

3. The device of claim 2 , wherein:

the third interconnect extends in the first direction;

the semiconductor memory device further comprises, in the second interconnect layer, a fourth interconnect extending in a second direction, the second direction crossing the first direction; and

the second interconnect and the third interconnect are coupled via the fourth interconnect.

4. The device of claim 3 , further comprising:

a fifth sense amplifier;

a tenth interconnect coupled to the fifth sense amplifier and extending in the first direction in the second interconnect layer; and

a fifth latch circuit coupled to the tenth interconnect, without intervention of an interconnect extending in the second direction in the second interconnect layer.

5. The device of claim 2 , wherein a width of the third interconnect is greater than a width of the first interconnect.

6. The device of claim 2 , further comprising:

a fourth sense amplifier;

a ninth interconnect coupled to the fourth sense amplifier, the ninth interconnect extending in the first direction in the second interconnect layer, and having a seventh end surface crossing the first direction; and

a fourth latch circuit coupled to the ninth interconnect,

wherein the third interconnect extends in the first direction and has an eighth end surface crossing the first direction, and

wherein the eighth end surface is opposed to the seventh end surface.

7. The device of claim 6 , wherein a width of the third interconnect is equal to a width of the ninth interconnect.

8. The device of claim 1 , wherein a width of the first interconnect is equal to a width of the second interconnect.

9. The device of claim 1 , further comprising:

a shield interconnect for the second interconnect.

10. The device of claim 1 , further comprising:

an interconnect coupled in parallel to the second interconnect.

11. The device of claim 10 , further comprising:

a shield interconnect for the second interconnect.

12. The device of claim 1 , further comprising:

a second memory cell;

a fifth interconnect coupled to the second memory cell and extending in the first direction in the first interconnect layer;

a second sense amplifier coupled to the fifth interconnect; and

a second latch circuit coupled to the second sense amplifier via the second interconnect.

13. The device of claim 12 , further comprising:

a third interconnect in a second interconnect layer, the second interconnect layer being at a position different from the first interconnect layer when viewed in a stacking direction,

wherein the first sense amplifier and the second interconnect are coupled via the third interconnect, and

wherein the second sense amplifier and the second interconnect are coupled via the third interconnect.

14. The device of claim 12 , wherein:

the fifth interconnect has a third end surface crossing the first direction; and

the third end surface and the first end surface are aligned along a second direction, the second direction crossing the first direction.

15. The device of claim 12 , further comprising:

a sixth interconnect extending in the first direction in the first interconnect layer and having a fourth end surface crossing the first direction,

wherein the fifth interconnect has a third end surface crossing the first direction,

wherein the third end surface is opposed to the fourth end surface, and

wherein the sixth interconnect is a shield interconnect.

16. The device of claim 15 , wherein the fourth end surface and the second end surface are aligned along a second direction, the second direction crossing the first direction.

17. The device of claim 12 , further comprising:

a sixth interconnect extending in the first direction in the first interconnect layer and having a fourth end surface crossing the first direction,

wherein the fifth interconnect has a third end surface crossing the first direction,

wherein the third end surface is opposed to the fourth end surface, and

wherein the second interconnect and the sixth interconnect being are coupled in parallel.

18. The device of claim 17 , wherein the fourth end surface and the second end surface are aligned along a second direction, the second direction crossing the first direction.

19. The device of claim 17 , further comprising:

a third memory cell;

a seventh interconnect coupled to the third memory cell, the seventh interconnect extending in the first direction in the first interconnect layer, and having a fifth end surface crossing the first direction;

a third sense amplifier coupled to the seventh interconnect;

a third latch circuit coupled to the third sense amplifier via the second interconnect; and

an eighth interconnect extending in the first direction in the first interconnect layer and having a sixth end surface crossing the first direction,

wherein the fifth end surface is opposed to the sixth end surface, and

wherein the eighth interconnect is a shield interconnect.