DATA TRANSMISSION FRAMING
Techniques for framing data in various data transmission contexts are described. A data framing technique may include a transmitter sending a data stream including repeating bits in alternating forward and reverse order. A receiver of the data stream may fold the data stream, and correlate portions of the folded data stream for purposes of validating the data stream and/or identifying an ID in the data stream. In at least some instances, once the receiver validates the data stream, the receiver may accept payload accompanying the data stream.
1 . A data transmitter, comprising:
first circuitry configured to transmit a stream of data including repeating alternating instances of a first data portion in a forward order and a second data portion representing a reverse order of the first data portion.
2 . The data transmitter of claim 1 , wherein the first data portion comprises 127 bits.
3 . The data transmitter of claim 1 , wherein the stream comprises a 0 or 1 bit between the first and second data portions.
4 . The data transmitter of claim 3 , wherein the first data portion is located previous and adjacent to the second data portion in the stream.
5 . The data transmitter of claim 3 , wherein the first data portion is located subsequent and adjacent to the second data portion in the stream.
6 . The data transmitter of claim 3 , wherein a first repeating alternating instance of the first and second data portions comprises 255 bits.
7 . The data transmitter of claim 1 , wherein the second data portion comprises an inverted representation of the reverse order of the first data portion.
8 . The data transmitter of claim 7 , wherein the inverted representation encodes the stream.
9 . A data receiver, comprising:
circuitry configured to receive a stream of data including repeating alternating instances of a first data portion in a forward order and a second data portion representing a reverse order of the first data portion, and correlate the first data portion with the second data portion.
10 . The data receiver of claim 9 wherein the circuitry is further configured to:
identify a palindrome sequence using the stream.
11 . The data receiver of claim 9 , wherein the first data portion comprises 127 bits.
12 . The data receiver of claim 9 , wherein the stream comprises a 0 or 1 bit between the first and second data portions.
13 . The data receiver of claim 12 , wherein the first data portion is located previous and adjacent to the second data portion in the stream.
14 . The data receiver of claim 12 , wherein the first data portion is located subsequent and adjacent to the second data portion in the stream.
15 . The data receiver of claim 12 , wherein a first repeating alternating instance of the first and second data portions comprises 255 bits.
16 . The data receiver of claim 9 , wherein the data receiver accepts payload after correlating the first data portion with the second data portion.
17 . The data receiver of claim 9 , wherein the circuitry is further configured to:
correlate the first data portion with the second data portion in a shift register.
18 . The data receiver of claim 17 , wherein:
the shift register comprises a fold point; and
the circuitry comprises a XNOR gate configured to compare bits one position way from the fold point.
19 . The data receiver of claim 9 , wherein the second data portion comprises an inverted representation of the reverse order of the first data portion.
20 . The data receiver of claim 19 , wherein the inverted representation encodes the stream.