Methods and apparatus to tile walk a tensor for convolution operations

1. An apparatus to perform a convolution on an input tensor, the apparatus comprising:

a parameters generator to:

generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on at least one of a kernel parameter or a layer parameter; and

generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on at least one of the kernel parameter or the layer parameter;

an accelerator interface to configure hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters;

a horizontal iterator controller to determine when the hardware accelerator circuitry completes a first horizontal iteration of the convolution; and

a vertical iterator controller to determine when the hardware accelerator circuitry completes a first vertical iteration of the convolution, at least one of the parameters generator, the accelerator interface, the horizontal iterator controller, or the vertical iterator controller to include circuitry.

2. The apparatus of claim 1 , wherein the layer parameter includes an input dimension sizes parameter of the input tensor, the kernel parameter includes a tile dimension sizes parameter of a tile of the input tensor, the accelerator interface to configure the hardware accelerator circuitry based on an input depth size parameter of a micro-tile of the tile.

3. The apparatus of claim 1 , wherein the horizontal hardware execution parameter is to configure the hardware accelerator circuitry to perform the first horizontal iteration of the convolution, and the vertical hardware execution parameter is to configure the hardware accelerator circuitry to perform the first vertical iteration of the convolution.

4. The apparatus of claim 1 , wherein:

the parameters generator is to generate a depth hardware execution parameter for a depth dimension of a micro-tile of the input tensor based on at least one of the kernel parameter or the layer parameter; and

the accelerator interface is to configure the hardware accelerator circuitry to perform the convolution based on the depth hardware execution parameter.

5. The apparatus of claim 4 , further including a depth iterator controller to determine when the hardware accelerator circuitry completes a first depth iteration of the convolution, the parameters generator to generate an updated depth hardware execution parameter when the hardware accelerator circuitry completes the first depth iteration of the convolution, the updated depth hardware execution parameter to configure the hardware accelerator circuitry to perform a second depth iteration of the convolution.

6. The apparatus of claim 1 , wherein:

the parameters generator is further to:

generate an updated horizontal hardware execution parameter when the hardware accelerator circuitry completes a horizontal iteration; and

generate an updated vertical hardware execution parameter when the hardware accelerator circuitry completes a vertical iteration of the convolution; and

the accelerator interface is further to:

configure the updated horizontal hardware execution parameter in the hardware accelerator circuitry to perform a second horizontal iteration of the convolution; and

configure the updated vertical hardware execution parameter in the hardware accelerator circuitry to perform a second vertical iteration of the convolution.

7. The apparatus of claim 1 , further including a graph compiler to generate the kernel parameter based on the layer parameter of the input tensor.

8. The apparatus of claim 1 , further including:

the hardware accelerator circuitry; and

a programmable controller in communication with the hardware accelerator circuitry, the programmable controller including the parameters generator, the accelerator interface, the horizontal iterator controller, and the vertical iterator controller.

9. A non-transitory computer readable storage medium comprising instructions that, when executed by a controller, cause the controller to at least:

generate a horizontal hardware execution parameter for a horizontal dimension of an input tensor based on at least one of a kernel parameter or a layer parameter;

generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on at least one of the kernel parameter or the layer parameter;

configure hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters;

determine when the hardware accelerator circuitry completes a first horizontal iteration of a convolution; and

determine when the hardware accelerator circuitry completes a first vertical iteration of the convolution.

10. The non-transitory computer readable storage medium as defined in claim 9 , wherein the layer parameter includes an input dimension sizes parameter of the input tensor, the kernel parameter includes a tile dimension sizes parameter of a tile of the input tensor, the instructions to cause the controller to configure the hardware accelerator circuitry based on an input depth size parameter of a micro-tile of the tile.

11. The non-transitory computer readable storage medium as defined in claim 9 , wherein the horizontal hardware execution parameter is to configure the hardware accelerator circuitry to perform the first horizontal iteration of the convolution, and the vertical hardware execution parameter is to configure the hardware accelerator circuitry to perform the first vertical iteration of the convolution.

12. The non-transitory computer readable storage medium as defined in claim 9 , wherein the instructions are further to cause the controller to:

generate a depth hardware execution parameter for a depth dimension of a micro-tile of the input tensor based on at least one of the kernel parameter or the layer parameter; and

configure the hardware accelerator circuitry to perform the convolution based on the depth hardware execution parameter.

13. The non-transitory computer readable storage medium as defined in claim 12 , wherein the instructions are further to cause the controller to:

determine when the hardware accelerator circuitry completes a first depth iteration of the convolution; and

generate an updated depth hardware execution parameter when the hardware accelerator circuitry completes the first depth iteration of the convolution, the updated depth hardware execution parameter to configure the hardware accelerator circuitry to perform a second depth iteration of the convolution.

14. The non-transitory computer readable storage medium as defined in claim 9 , wherein the instructions are further to cause the controller to:

generate an updated horizontal hardware execution parameter when the hardware accelerator circuitry completes a horizontal iteration;

generate an updated vertical hardware execution parameter when the hardware accelerator circuitry completes a vertical iteration of the convolution;

configure the updated horizontal hardware execution parameter in the hardware accelerator circuitry to perform a second horizontal iteration of the convolution; and

configure the updated vertical hardware execution parameter in the hardware accelerator circuitry to perform a second vertical iteration of the convolution.

15. The non-transitory computer readable storage medium as defined in claim 9 , wherein the instructions are further to cause the controller to generate the kernel parameter based on the layer parameter of the input tensor.

16. A method to perform a convolution on an input tensor, the method comprising:

generating a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on at least one of a kernel parameter or a layer parameter;

generating a vertical hardware execution parameter for a vertical dimension of the input tensor based on at least one of the kernel parameter or the layer parameter;

configuring hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters;

determining when the hardware accelerator circuitry completes a first horizontal iteration of the convolution; and

determining when the hardware accelerator circuitry completes a first vertical iteration of the convolution.

17. The method as defined in claim 16 , wherein the layer parameter includes an input dimension sizes parameter of the input tensor, the kernel parameter includes a tile dimension sizes parameter of a tile of the input tensor, the configuring of the hardware accelerator circuitry based on an input depth size parameter of a micro-tile of the tile.

18. The method as defined in claim 16 , wherein the horizontal hardware execution parameter is to configure the hardware accelerator circuitry to perform the first horizontal iteration of the convolution, and the vertical hardware execution parameter is to configure the hardware accelerator circuitry to perform the first vertical iteration of the convolution.

19. The method as defined in claim 16 , further including:

generating a depth hardware execution parameter for a depth dimension of a micro-tile of the input tensor based on at least one of the kernel parameter or the layer parameter; and

configuring the hardware accelerator circuitry to perform the convolution based on the depth hardware execution parameter.

20. The method as defined in claim 19 , further including:

determining when the hardware accelerator circuitry completes a first depth iteration of the convolution; and

generating an updated depth hardware execution parameter when the hardware accelerator circuitry completes the first depth iteration of the convolution, the updated depth hardware execution parameter to configure the hardware accelerator circuitry to perform a second depth iteration of the convolution.

21. The method as defined in claim 16 , further including:

generating an updated horizontal hardware execution parameter when the hardware accelerator circuitry completes a horizontal iteration;

generating an updated vertical hardware execution parameter when the hardware accelerator circuitry completes a vertical iteration of the convolution;

configuring the updated horizontal hardware execution parameter in the hardware accelerator circuitry to perform a second horizontal iteration of the convolution; and

configuring the updated vertical hardware execution parameter in the hardware accelerator circuitry to perform a second vertical iteration of the convolution.

22. The method as defined in claim 16 , further including generating the kernel parameter based on the layer parameter of the input tensor.

23. An apparatus to perform a convolution on an input tensor, the apparatus comprising:

means for generating parameters to:

generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on at least one of a kernel parameter or a layer parameter; and

generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on at least one of the kernel parameter or the layer parameter;

means for configuring means for performing convolutions based on the horizontal and vertical hardware execution parameters;

means for controlling a horizontal iterator to determine when the means for performing convolutions completes a first horizontal iteration of the convolution; and

means for controlling a vertical iterator to determine when the means for performing convolutions completes a first vertical iteration of the convolution.

24. The apparatus of claim 23 , wherein the layer parameter includes an input dimension sizes parameter of the input tensor, the kernel parameter includes a tile dimension sizes parameter of a tile of the input tensor, the means for configuring to use an input depth size parameter of a micro-tile of the tile to configure the means for performing convolutions.

25. The apparatus of claim 23 , wherein the horizontal hardware execution parameter is to configure the means for performing convolutions to perform the first horizontal iteration of the convolution, and the vertical hardware execution parameter is to configure the means for performing convolutions to perform the first vertical iteration of the convolution.

26. The apparatus of claim 23 , wherein:

the means for generating parameters is to generate a depth hardware execution parameter for a depth dimension of a micro-tile of the input tensor based on at least one of the kernel parameter or the layer parameter; and

the means for configuring the means for performing convolutions is to configure the means for performing convolutions to perform the convolution based on the depth hardware execution parameter.

27. The apparatus of claim 26 , further including means for controlling a depth iterator to determine when the means for performing convolutions completes a first depth iteration of the convolution, the means for generating parameters to generate an updated depth hardware execution parameter when the means for performing convolutions completes the first depth iteration of the convolution, the updated depth hardware execution parameter to configure the means for performing convolutions to perform a second depth iteration of the convolution.

28. The apparatus of claim 23 , wherein:

the means for generating parameters is further to:

generate an updated horizontal hardware execution parameter when the means for performing convolutions completes the first horizontal iteration of the convolution; and

generate an updated vertical hardware execution parameter when the means for performing convolutions completes the first vertical iteration of the convolution; and

means for configuring the means for performing convolutions is to:

configure the updated horizontal hardware execution parameter in the means for performing convolutions to perform a second horizontal iteration of the convolution; and

configure the updated vertical hardware execution parameter in the means for performing convolutions to perform a second vertical iteration of the convolution.

29. The apparatus of claim 23 , further including means for generating the kernel parameter based on the layer parameter of the input tensor.