IP Library Granted Patent US 11,675,630
Granted Patent B2
US 11,675,630 · App. 16/541,979 · Granted Jun 13, 2023

Methods and apparatus to configure heterogenous components in an accelerator

Inventors: Michael Behar (Zichron Yaakov, IL); Moshe Maor (Kiryat Mozking, IL); Ronen Gabbai (Ramat Hashofet, IL); Roni Rosner (Binyamina, IL); Zigi Walter (Haifa, IL); Oren Agam (Zichron Yaacov, IL)
Assignee: INTEL CORPORATION
G06F9/5083G06F16/9024G06N3/044G06N3/045
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,675,630
App. No.
16/541,979
Granted
Jun 13, 2023
Kind
B2
Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

Claims (63)

1. An apparatus to configure heterogenous components in an accelerator, the apparatus comprising:

a graph compiler to:

identify a workload node in a workload; and

generate a selector for the workload node; and

the selector to:

identify an input condition of a compute building block, the input condition to describe a number of inputs accepted by a kernel executing on the compute building block; and

identify an output condition of the compute building block, the output condition to describe one or more of: (a) a number of outputs generated by the kernel, and (b) types of data structures generated by the kernel, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

2. The apparatus of claim 1 , wherein the graph compiler is to:

identify a second workload node in the workload; and

generate a second selector for the second workload node.

3. The apparatus of claim 2 , wherein:

the compute building block is a first building block in the accelerator; and

the second selector is to identify a second input condition and a second output condition of a second compute building block.

4. The apparatus of claim 1 , wherein the workload is a graph including the workload node obtained by the graph compiler.

5. The apparatus of claim 1 , wherein the input condition corresponds to an input requirement of the compute building block and the output condition corresponds to a result of execution of the compute building block.

6. The apparatus of claim 1 , wherein the graph compiler is to generate an executable file in response to mapping the workload node to the compute building block.

7. The apparatus of claim 1 , wherein the graph compiler further includes a plugin to, based on the identified input condition and output condition, form a translation layer between the workload node and the compute building block to enable mapping of the workload node to the compute building block.

8. At least one non-transitory computer readable storage medium comprising instructions which, when executed, cause at least one processor to at least:

identify a workload node in a workload;

generate a selector for the workload node, the selector associated with a compute building block to execute the workload node;

identify an input condition of the compute building block, the input condition to describe types of data structures accepted by a kernel executing on the compute building block;

identify an output condition of the compute building block, the output condition to describe one or more of: (a) a number of outputs generated by the kernel, and (b) types of data structures generated by the kernel; and

in response to obtaining the identified input condition and output condition, map the workload node to the compute building block.

9. The at least one non-transitory computer readable storage medium of claim 8 , wherein the instructions, when executed, further cause the at least one processor:

identify a second workload node in the workload; and

generate a second selector for the second workload node.

10. The at least one non-transitory computer readable storage medium of claim 9 , wherein:

the compute building block is a first compute building block in an accelerator; and

the instructions, when executed, further cause the at least one processor to identify a second input condition and a second output condition of a second compute building block in the accelerator.

11. The at least one non-transitory computer readable storage medium of claim 8 , wherein the workload is a graph including the workload node.

12. The non-transitory computer readable storage medium of claim 8 , wherein the input condition corresponds to an input requirement of the compute building block and the output condition corresponds to a result of execution of the compute building block.

13. The at least one non-transitory computer readable storage medium of claim 8 , wherein the instructions, when executed, further cause the at least one processor to generate an executable file in response to mapping the workload node to the compute building block.

14. The at least one non-transitory computer readable storage medium of claim 8 , wherein the instructions, when executed, further cause the at least one processor to, based on the identified input condition and output condition, form a translation layer between the workload node and the compute building block to enable mapping of the workload node to the compute building block.

15. An apparatus to configure heterogenous components in an accelerator, the apparatus comprising:

means for compiling to:

identify a workload node in a workload; and

generate a means for selecting for the workload node, the means for selecting associated with a compute building block to execute the workload node; and

the means for selecting to:

identify an input condition of the compute building block, the input condition to describe an amount of memory a kernel executing on the compute building block can allocate to a workload; and

identify an output condition of the compute building block, the output condition to describe one or more of: (a) a number of outputs generated by the kernel, and (b) types of data structures generated by the kernel, wherein the means for compiling is further to, in response to obtaining the identified input condition and output condition, map the workload node to the compute building block.

16. The apparatus of claim 15 , wherein the means for compiling is further to:

identify a second workload node in the workload; and

generate a second means for selecting for the second workload node.

17. The apparatus of claim 16 , wherein:

the compute building block is a first compute building block in the accelerator; and

the second means for selecting is further to identify a second input condition and a second output condition of a second compute building block in the accelerator.

18. The apparatus of claim 15 , wherein the workload is a graph including the workload node.

19. The apparatus of claim 15 , wherein the input condition corresponds to an input requirement of the compute building block and the output condition corresponds to a result of execution of the compute building block.

20. The apparatus of claim 15 , wherein the means for compiling is further to generate an executable file in response to mapping the workload node to the compute building block.

21. The apparatus of claim 15 , wherein the means for compiling is further to, based on the identified input condition and output condition, form a translation layer between the workload node and the compute building block to enable mapping of the workload node to the compute building block.

22. A method to configure heterogenous components in an accelerator, the method comprising:

identifying a workload node in a workload;

generating a selector for the workload node, the selector associated with a compute building block to execute the workload node;

identifying an input condition of the compute building block, the input condition to describe one or more of: (a) a number of inputs accepted by a kernel executing on the compute building block, (b) types of data structures accepted by the kernel, and (c) an amount of memory the kernel can allocate in the compute building block to a workload;

identify an output condition of the compute building block, the output condition to describe one or more of: (a) a number of outputs generated by the kernel, and (b) types of data structures generated by the kernel; and

in response to obtaining the identified input condition and output condition, mapping the workload node to the compute building block.

23. The method of claim 22 , further including:

identifying a second workload node in the workload; and

generating a second selector for the second workload node.

24. The method of claim 23 , wherein:

the compute building block is a first compute building block in the accelerator; and

the method further includes identifying a second input condition and a second output condition of a second compute building block in the accelerator.

25. The method of claim 22 , wherein the workload is a graph including the workload node.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2019
From: BEHAR, MICHAEL; MAOR, MOSHE; GABBAI, RONEN; ROSNER, RONI; WALTER, ZIGI; AGAM, OREN
To: INTEL CORPORATION
Reel/Frame 050353/0650 →
Continuity (1)
Related Publication 20190370084A1 · Dec 5, 2019
Cited By (1)
US 12,223,319