Methods for independent memory bank maintenance and memory devices and systems employing the same
Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
1. A memory module comprising:
a plurality of memory devices, each memory device including a plurality of memory banks; and
circuitry configured to:
store a plurality of values, each value of the plurality of values corresponding to one memory bank of the plurality of memory banks of one of the plurality of memory devices, and
in response to first data stored in a first memory bank of the plurality of memory banks of a first memory device of the plurality of memory devices being refreshed, update a first value of the plurality of values corresponding to the first memory bank of the first memory device based at least in part on refreshing the first data.
2. The memory module of claim 1 , wherein the circuitry is further configured to:
subsequent to the first data being refreshed, and before data stored in all of the other memory banks of the plurality of memory banks of the first memory device is refreshed, update the first value of the plurality of values based at least in part on second data in the first memory bank being refreshed.
3. The memory module of claim 2 , wherein the second data corresponds to a second row of the first memory bank.
4. The memory module of claim 1 , wherein the first data corresponds to a first row of the first memory bank.
5. The memory module of claim 1 , wherein each of the plurality of values corresponds to a row address in a corresponding memory bank of the plurality of memory banks of one of the plurality of memory devices.
6. The memory module of claim 5 , wherein the circuitry is configured to update the first value of the plurality of values by replacing the row address of the refreshed first data with another row address of the first memory bank.
7. The memory module of claim 1 , wherein the circuitry is further configured to:
update a second value of the plurality of values corresponding to the second memory bank based at least in part on refreshing second data stored in a second memory bank of the plurality of memory banks of the first memory device.
8. The memory module of claim 1 , wherein the circuitry is further configured to:
update a second value of the plurality of values corresponding to the second memory bank based at least in part on refreshing second data stored in a second memory bank of the plurality of memory banks of a second memory device of the plurality of memory devices.
9. The memory module of claim 1 , wherein the circuitry is external to the plurality of memory devices.
10. The memory module of claim 1 , wherein the plurality of memory devices comprise dynamic random access memory (DRAM) devices, ferroelectric random access memory (FeRAM) devices, magnetoresistive memory (MRAM) devices, phase change memory (PCM) devices, or a combination thereof.
11. A memory system, comprising:
a plurality of memory devices; and
circuitry configured to:
store a plurality of counters, each value of the plurality of counters corresponding to one memory bank of a plurality of memory banks of one of the plurality of memory devices,
update, in response to first data stored in a first memory bank of the plurality of memory banks of a first memory device of the plurality of memory devices being refreshed, a first counter of the plurality of counters corresponding to the first memory bank.
12. The memory system of claim 11 , wherein the circuitry is configured to update the first counter of the plurality of counters by writing a row address corresponding to the first data to the first counter.
13. The memory system of claim 11 , wherein the circuitry is further configured to:
update, in response to refreshing second data stored in a second memory bank of the plurality of memory banks of the first memory device, a second counter of the plurality of counters corresponding to the second memory bank.
14. The memory system of claim 13 , wherein updating the second counter of the plurality of counters corresponding to the second memory bank comprises writing a row address corresponding to the second data to the second counter.
15. The memory system of claim 11 , wherein the circuitry is further configured to:
update, in response to refreshing second data stored in a second memory bank of the plurality of memory banks of a second memory device of the plurality of memory devices, a second counter of the plurality of counters corresponding to the second memory bank.
16. The memory system of claim 11 , wherein the plurality of counters is stored in counter circuitry of a memory module to which the plurality of memory devices is operably connected to.
17. The memory system of claim 11 , wherein the plurality of counters is stored in a host device operably connected to the plurality of memory devices.
18. The memory system of claim 17 , wherein refreshing the first data is performed in response to the host device sending a command instructing the first memory device to perform a refresh operation on only the first one of the plurality of memory banks of the first memory device.
19. The memory system of claim 17 , wherein refreshing the first data is performed in response to the host device sending a command instructing the first memory device to perform a refresh operation on less than all of the plurality of memory banks of the first memory device.
20. The memory system of claim 11 , wherein the plurality of memory devices comprise dynamic random access memory (DRAM) devices, ferroelectric random access memory (FeRAM) devices, magnetoresistive memory (MRAM) devices, phase change memory (PCM) devices, or a combination thereof.