Flexible baud rate

1. An apparatus enabled to selectively choose a baud rate for communication of coherent optical data; the apparatus comprising:

a modem enabled to operate with a coherent optical signal modulated at a plurality of finely tuned baud rates; wherein the modem is enabled to finely tune a baud rate to optimize the baud rate to utilize an available passband of an optical link for communication of optical data; wherein the plurality of finely tuned baud rates refers to baud rates with a relative increase of baud-rate from one baud-rate to the next being smaller than 10%; wherein the baud rate is enabled to be adjusted in a range including 24.0 to 72.0 GBd.

2. The apparatus of claim 1 , wherein the modem includes a digital signal processor (DSP); wherein the DSP interpolates digital data samples received by the modem from a first sample rate to a second sample rate.

3. The apparatus of claim 2 , wherein the second sample rate accommodates to a sampling rate of a DAC, wherein the sampling rate of the DAC is fixed.

4. The apparatus of claim 2 , wherein the first sample rate accommodates to a sampling rate of an ADC, wherein the sampling rate of the ADC is fixed; and wherein the second sample rate is a target sampling rate that is different from the first sample rate.

5. The apparatus of claim 2 , wherein the interpolation of the DSP uses a numerically-controlled oscillator (NCO).

6. The apparatus of claim 1 , wherein the modem includes a clock; wherein the speed of the clock of an ADC/DAC is changed to match a sampling rate.

7. The apparatus of claim 2 wherein the DSP has an interpolator and a numerically controlled oscillator; wherein the numerically controlled oscillator provides the interpolator with sampling timing; wherein the interpolator creates output samples based on the sampling timing.

8. The apparatus of claim 7 wherein the output samples are used to drive a DAC.

9. The apparatus of claim 7 wherein input samples are received from an ADC.

10. The apparatus of claim 6 wherein the clock is changed by a phase locked loop (PLL).

11. The apparatus of claim 1 , wherein the modem is adapted to switch between different QAM encoding formats, and wherein the baud rate is changed when switching from one QAM encoding format to a different QAM encoding format.

12. The apparatus of claim 1 , wherein the plurality of finely tuned baud rates includes neighboring baud rates with a difference of baud rates of less than 3%, 2%, 1%, 0.5%, 0.3%, or 0.1% of the overall baud rate.

13. The apparatus of claim 1 , wherein the plurality of finely tuned baud rates refers to baud rates with a relative increase of baud-rate from one baud-rate to the next being smaller than 10%, 5%, 3%, or 1%.

14. A method to selectively choose a baud rate for communication of coherent optical data; the method comprising:

enabling a modem to operate with a coherent optical signal modulated at a plurality of finely tuned baud rates; and

finely tune the baud rate to optimize a baud rate to utilize an available passband of an optical link for communication of the optical data; wherein the plurality of finely tuned baud rates refers to baud rates with a relative increase of baud-rate from one baud-rate to the next being smaller than 10%; wherein the baud rate is enabled to be adjusted in a range including from 24.0 to 72.0 GBd.

15. The method of claim 14 , wherein the modem includes a digital signal processor (DSP); wherein the method further includes:

interpolating, by the DSP, digital data samples received by the modem from a first sample rate to a second sample rate to match the second sample rate to accommodate a sampling rate of the ADC/DAC.

16. The method of claim 14 , wherein the modem includes a clock; the method further comprising:

changing the speed of the clock of an ADC/DAC to match a sampling rate.

17. The method of claim 14 wherein the DSP has an interpolator and a numerically controlled oscillator; wherein the method further includes:

providing the interpolator with sampling timing from the numerically controlled oscillator; and

creating output samples, by the interpolator, based on the sampling timing.

18. The method of claim 17 wherein the output samples are used to drive a DAC.

19. The method of claim 17 wherein input samples are received from an ADC.

20. The method of claim 16 wherein the clock is changed by a phase locked loop (PLL).