Fault diagnostics

1. A method, comprising:

receiving a layout of a circuit, the layout comprising a first cell and a second cell separated by a boundary circuit;

determining bridge pairs for the circuit, the bridge pairs comprising a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell;

connecting one of the first plurality of boundary nodes to a pre-determined potential to model bridge pair faults between the bridge pairs; and

generating a test pattern for the bridge pair faults.

2. The method of claim 1 , further comprising determining a fault coverage of the circuit from the test pattern.

3. The method of claim 2 , further comprising inserting, in response to determining that the fault coverage is less than a predetermined level, a filler cell between the first cell and the second cell.

4. The method of claim 3 , further comprising determining the bridge pairs for the circuit with the inserted filler cell.

5. The method of claim 1 , wherein modeling the bridge pair faults between the bridge pairs comprises modelling the bridge pair faults between internal node to internal node bridge pairs.

6. The method of claim 1 , wherein modeling the bridge pair faults between the bridge pairs comprises modelling the bridge pair faults between internal node to external node bridge pairs.

7. The method of claim 1 , wherein modeling the bridge pair faults between the bridge pairs comprises modelling the bridge pair faults as individual cell level faults.

8. The method of claim 1 , wherein generating the test pattern for the bridge pair faults comprises generating an input pattern and an expected output for the input pattern for each of the bridge pair faults.

9. The method of claim 1 , wherein modeling the bridge pair faults between the bridge pairs comprises modelling dynamic faults in the bridge pairs.

10. A non-transitory computer-readable medium that stores a set of instructions when executed perform a method, the method comprising:

receiving a layout of a circuit, the layout comprising a position and an orientation of a plurality of cells of the circuit;

determining bridge pairs between neighboring cells of the plurality of cells of the circuit, the bridge pairs comprising a first plurality of boundary nodes paired with a second plurality of boundary nodes, wherein determining the bridge pairs comprises:

determining a first cell and a second cell abutting the first cell,

determining a cell layout for each of the first cell and the second cell,

determining a base orientation for each of the first cell and the second cell from the cell orientation, and

determining, from the base orientation, the first plurality of boundary nodes of the first cell facing one of the second plurality of boundary nodes of the second cell;

modeling bridge pair faults between the bridge pairs; and

generating a test pattern for the bridge pair faults.

11. The non-transitory computer-readable medium of claim 10 , wherein each of the first plurality of boundary nodes and the second plurality of boundary nodes comprises at least one of an internal node, an external node, a power ground node, and an input/output node.

12. The non-transitory computer readable medium of claim 11 , wherein modeling the bridge pair faults between the bridge pairs comprises modeling the bridge pair faults between at least one of internal node to internal node bridge pairs and internal node to external node bridge pairs.

13. The non-transitory computer readable medium of claim 11 , wherein modeling the bridge pair faults between the bridge pairs comprises modeling the bridge pair faults at the first cell level.

14. An apparatus comprising:

a memory storage; and

a processing unit coupled to the memory storage, wherein the processing unit is operative to:

receive a layout of a circuit, the layout comprising a first cell and a second cell separated by a boundary circuit;

determine a bridge pair for the circuit, the bridge pair comprising a first boundary node of the first cell paired with a second boundary node of the second cell;

connect the first boundary node to a pre-determined potential to model a bridge pair fault between the bridge pair; and

generate a test pattern for the bridge pair fault.

15. The apparatus of claim 14 , wherein the processing unit is further operative to determine a fault coverage of the circuit from the generated test pattern.

16. The apparatus of claim 15 , wherein the processing unit is further operative to insert, in response to determining that the fault coverage is less than a predetermined level, a filler cell between the first cell and the second cell.

17. The apparatus of claim 16 , wherein the processing unit is further operative to determine the bridge pair for the circuit with the inserted filler cell.

18. The apparatus of claim 14 , wherein the processing unit being operative to model the bridge pair fault between the bridge pair comprises the processing unit being operative to model the bridge pair fault between an internal node to internal node bridge pair.

19. The apparatus of claim 14 , wherein the processing unit being operative to model the bridge pair fault between the bridge pair comprises the processing unit being operative to model the bridge pair fault between an internal node to external node bridge pair.

20. The apparatus of claim 14 , wherein the processing unit being operative to model the bridge pair fault between the bridge pair comprises the processing unit being operative to model the bridge pair fault as an individual cell level fault.