IP Library Granted Patent US 10,634,620
Granted Patent B2
US 10,634,620 · App. 16/546,179 · Granted Apr 28, 2020

Methods, test structures, and test systems for determining a surface characteristic of a chip facet

Inventors: Matthew Akio Streshinsky (New York, NY); Ari Novack (New York, NY); Michael J. Hochberg (New York, NY)
Assignee: Elenion Technologies, LLC
G01N21/8806G01B11/30G01R31/311H01L22/12H01L22/30G01R31/308
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Quick Facts
Patent No.
US 10,634,620
App. No.
16/546,179
Granted
Apr 28, 2020
Kind
B2
Abstract

A test system for determining a surface characteristic of a chip facet comprises a chip, which has a facet and includes a waveguide, a detector, and a processor. The on-chip waveguide is configured to direct test light towards the facet, where a portion of the test light is reflected and a portion of the test light is transmitted. The detector is configured to measure an amount of the reflected portion or the transmitted portion, and the processor is configured to determine a surface characteristic of the facet, such as a facet angle, a facet curvature, and/or a facet roughness, on the basis of the measured amount.

Claims (21)

1. A photonic chip comprising:

a facet configured for providing optical coupling to the photonic chip;

a first waveguide configured to direct test light towards the facet;

a second waveguide configured to receive a reflected portion of the test light reflected or scattered from the facet; and,

an output test port for coupling the reflected portion of the test light to a photodetector for determining a characteristic of the facet;

wherein the first waveguide and the second waveguide are monolithically integrated in the photonic chip.

2. The photonic chip of claim 1 further comprising an input test port for coupling the test light into the first waveguide.

3. The photonic chip of claim 2 comprising a main face intersected by the facet, wherein the first and second waveguides are disposed to guide the test light generally parallel to the main face, and wherein at least one of the input and output test ports comprises a vertical coupler configured to couple the test light in or out of the photonic chip through the main face thereof.

4. The photonic chip of claim 1 wherein the first waveguide comprises an end disposed to receive the reflected portion of the test light from the facet, further comprising an optical coupler disposed to couple the reflected portion of the test light from the first waveguide into the second waveguide.

5. The photonic chip of claim 4 comprising an on-chip Michelson interferometer formed with the optical coupler, the on-chip Michelson interferometer comprising a phase shifter and a reflector in one arm thereof.

6. The photonic chip of claim 1 comprising a main face intersected by the facet, wherein the first and second waveguides are disposed parallel to the main face at different heights therefrom.

7. The photonic chip of claim 6 comprising a diffraction grating disposed at an end of one of the first or second waveguides proximate to the facet for coupling the reflect portion of the test light into the first or second waveguide.

8. The photonic chip of claim 1 comprising a micro-ring resonator disposed adjacent to the facet to couple the test light from the first waveguide into the second waveguide in dependence on the characteristic of the facet.

9. The photonic chip of claim 1 further comprising a photodetector disposed to receive the reflected portion of the test light.

10. A test system for testing a facet characteristic of the photonic chip of claim 1 , comprising a photodetector disposed to receive the reflected portion of the test light from the second waveguide, and a processor configured to determine the facet characteristic based at least in part on a signal produced by the photodetector responsive to receiving the reflect portion of the test light.

11. A photonic chip comprising:

a facet configured for providing optical coupling to the photonic chip, the facet comprising a top edge defined at a main face of the photonic chip; and

a plurality of waveguide test structures comprising test segments disposed at varying positions relative to the top edge, each of the waveguide test structures comprising at least one optical port for coupling test light out of the test structure after transmission through the test segment;

wherein the transmission of the test light through at least some of the test segments depends on a characteristic of the facet.

12. The photonic chip of claim 11 wherein the test segments are disposed substantially parallel to the top edge of the facet.

13. The photonic chip of claim 11 wherein the characteristic of the facet is a facet angle relative to the main face of the photonic chip.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2022
From: ELENION TECHNOLOGIES LLC
To: NOKIA SOLUTIONS AND NETWORKS OY
Reel/Frame 058708/0603 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2019
From: STRESHINSKY, MATTHEW AKIO; NOVACK, ARI; HOCHBERG, MICHAEL J.
To: ELENION TECHNOLOGIES, LLC
Reel/Frame 050108/0891 →
Continuity (2)
Continuation 15427185 · Feb 8, 2017
Related Publication 20190369029A1 · Dec 5, 2019