System and method for a single logical IP subnet across multiple independent layer 2 (L2) subnets in a high performance computing environment

1. A system for supporting a single logical IP subnet across multiple independent layer 2 subnets in a high performance computing environment, comprising:

a computer, the computer comprising one or more microprocessors;

a logical device, the logical device being addressed by a layer 3 address, wherein the logical device comprises a plurality of network adapters, each of the network adapters comprising a physical port; and

a plurality of switches including at least first, second, and third switches;

a first discrete layer 2 subnet connected to the first switch and second switch;

a second discrete layer 2 subnet connected to the third switch wherein the second discrete layer 2 subnet is independent of the first discrete layer 2 subnet;

wherein each of the first, second, and third switches is connected to a separate physical port of a network adapter of the plurality of network adapters of the logical device, wherein the first and second switches are interconnected via one or more control links; and

wherein a mapping table is provided at the logical device; and

wherein the logical device performs a load balancing function for packets addressed to the layer 3 address of the logical device by distributing said packets over the first discrete layer 2 subnet and the second discrete layer 2 subnet.

2. The system of claim 1 , wherein the logical device is addressed by one layer 3 address.

3. The system of claim 2 , wherein each of the physical ports on the logical device are addressed by at least a layer 2 address.

4. The system of claim 3 , wherein each of the physical ports on the logical device are further addressed by the layer 3 address of the logical device.

5. The system of claim 4 ,

wherein the first and second switches of the plurality of switches are arranged in a layer two subnet of the first discrete layer 2 subnet comprising a multi-chassis link aggregation scheme.

6. The system of claim 5 ,

wherein the third switch of the plurality of switches is arranged in a layer two subnet of the second discrete layer 2 subnet comprising a link aggregation scheme.

7. The system of claim 6 ,

wherein a packet comprising a source layer 2 address, a destination layer 2 address is received at the logical device;

wherein after receiving the packet, the logical device updates the destination layer 2 address of the received packet based upon the mapping table;

wherein the logical device forwards the updated packet on a physical port of the logical device; and

wherein the updated destination layer 2 address is associated with one of the layer two subnet comprising the multi-chassis link aggregation scheme and the layer two subnet comprising the link aggregation scheme.

8. A method for supporting a single logical IP subnet across multiple independent layer 2 subnets in a high performance computing environment, comprising:

providing, at a computer comprising one or more microprocessors; a logical device, the logical device being addressed by a layer 3 address, wherein the logical device comprises a plurality of network adapters, each of the network adapters comprising a physical port, and a plurality of switches including at least first, second, and third switches;

arranging the plurality of switches into a plurality of discrete layer 2 subnets, including a first discrete layer 2 subnet connected to the first switch and second switch; and

a second discrete layer 2 subnet connected to the third switch wherein the second discrete layer 2 subnet is independent of the first discrete layer 2 subnet;

connecting each of the first, second and third switches to a separate at least one physical port of a network adapter of the plurality of network adapters of the logical device;

interconnecting the first switch and second switch via one or more control links; and

providing a mapping table at the logical device;

wherein the logical device performs a load balancing function for packets addressed to the layer 3 address of the logical device by distributing said packets over the first discrete layer 2 subnet and the second discrete layer 2 subnet.

9. The method of claim 8 , wherein the logical device is addressed by one layer 3 address.

10. The method of claim 9 , wherein each of the physical ports on the logical device are addressed by at least a layer 2 address.

11. The method of claim 10 , wherein each of the physical ports on the logical device are further addressed by the layer 3 address of the logical device.

12. The method of claim 11 ,

wherein said first and second switches of the plurality of switches are arranged in a layer two subnet of the first discrete layer 2 subnet comprising a multi-chassis link aggregation scheme.

13. The method of claim 12 ,

wherein the third switch of the plurality of switches is arranged in a layer two subnet of the second discrete layer 2 subnet comprising a link aggregation scheme.

14. The method of claim 13 ,

wherein a packet comprising a source layer 2 address, a destination layer 2 address is received at the logical device;

wherein after receiving the packet, the logical device updates the destination layer 2 address of the received packet based upon the mapping table;

wherein the logical device forwards the updated packet on a physical port of the logical device; and

wherein the updated destination layer 2 address is associated with one of the layer two subnet comprising the multi-chassis link aggregation scheme and the layer two subnet comprising the link aggregation scheme.

15. A non-transitory computer readable storage medium having instructions thereon for supporting a single logical IP subnet across multiple independent layer 2 subnets in a high performance computing environment, which when read and executed by a computer cause the computer to perform steps comprising:

providing, at a computer comprising one or more microprocessors;

a logical device, the logical device being addressed by a layer 3 address, wherein the logical device comprises a plurality of network adapters, each of the network adapters comprising a physical port, and a plurality of switches including at least first, second, and third switches;

arranging the plurality of switches into a plurality of discrete layer 2 subnets, including a first discrete layer 2 subnet connected to the first switch and second switch, and a second discrete layer 2 subnet connected to the third switch wherein the second discrete layer 2 subnet is independent of the first discrete layer 2 subnet;

connecting each of the first, second, and third switches to at least one separate physical port of a network adapter of the plurality of network adapters of the logical device;

interconnecting the first switch and second switch via one or more control links; and

providing a mapping table at the logical device;

wherein the logical device performs a load balancing function for packets addressed to the layer 3 address of the logical device by distributing said packets over the first discrete layer 2 subnet and the second discrete layer 2 subnet.

16. The non-transitory computer readable storage medium of claim 15 , wherein the logical device is addressed by one layer 3 address.

17. The non-transitory computer readable storage medium of claim 16 , wherein each of the physical ports on the logical device are addressed by at least a layer 2 address.

18. The non-transitory computer readable storage medium of claim 17 , wherein each of the physical ports on the logical device are further addressed by the layer 3 address of the logical device.

19. The non-transitory computer readable storage medium of claim 18 ,

wherein said first and second switches of the plurality of switches are arranged in a layer two subnet of the first discrete layer 2 subnet comprising a multi-chassis link aggregation scheme.

20. The non-transitory computer readable storage medium of claim 19 ,

wherein the third switch of the plurality of switches is arranged in a layer two subnet of the second discrete layer 2 subnet comprising a link aggregation scheme;

wherein a packet comprising a source layer 2 address, a destination layer 2 address is received at the logical device;

wherein after receiving the packet, the logical device updates the destination layer 2 address of the received packet based upon the mapping table;

wherein the logical device forwards the updated packet on a physical port of the logical device; and

wherein the updated destination layer 2 address is associated with one of the layer two subnet comprising the multi-chassis link aggregation scheme and the layer two subnet comprising the link aggregation scheme.