Methods of forming NAND cell units
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.
1. A method of forming a NAND cell unit, comprising:
forming a select gate comprising gate material and electrically insulative material only partially covering the gate material and leaving an opening;
forming a first conductive material in the opening and a second conductive material in the opening; and
forming a string gate spaced from the select gate.
2. The method of claim 1 wherein the first conductive material contacts the gate material.
3. The method of claim 1 wherein the first and second conductive material fill the opening in the electrically insulative material.
4. The method of claim 1 wherein the string gate further comprises the electrically insulative material.
5. The method of claim 4 wherein the electrically insulative material of the string gate has no opening.
6. The method of claim 4 wherein the electrically insulative material comprises a plurality of discrete layers.
7. The method of claim 1 wherein the electrically insulative material comprises a plurality of discrete layers.
8. The method of claim 1 wherein the string gate comprises gate material different from the gate material of the select gate.
9. The method of claim 8 wherein the gate material for the string gate comprises one or more charge-trapping compositions.
10. The method of claim 1 wherein the gate material comprises conductively-doped silicon.
11. The method of claim 1 wherein the gate material comprises conductively-doped silicon, and wherein the first conductive material comprises at least one metal.
12. A method of forming a NAND cell unit, comprising:
forming a select gate comprising gate material and electrically insulative material only partially covering the gate material and leaving an opening;
forming a conductive liner in the opening and against at least one of the gate material and the electrically insulative material; and
forming a string gate spaced from the select gate.
13. The method of claim 12 wherein the conductive liner is against the gate material.
14. The method of claim 12 wherein the conductive liner is against the electrically insulative material.
15. The method of claim 12 wherein the conductive liner is against the gate material and against the electrically insulative material.
16. The method of claim 12 further comprising forming conductive material in the opening.
17. The method of claim 16 wherein the conductive material fills the opening.
18. The method of claim 12 wherein the string gate comprises the gate material.
19. The method of claim 12 wherein the string gate comprises the electrically insulative material.
20. The method of claim 12 wherein the string gate comprises:
the electrically insulative material; and
the gate material.