Memory system and information processing system
A memory system includes a nonvolatile memory, an interface circuit, and a controller configured to upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command, determine a compression ratio of each write data based on the acquired compression-ratio information, and determine an execution order of the write commands based on the determined compression ratio.
1. A memory system comprising:
a nonvolatile memory;
an interface circuit; and
a controller configured to
upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command,
determine a compression ratio of each write data based on the acquired compression-ratio information, and
determine an execution order of the write commands based on the determined compression ratio.
2. The memory system according to claim 1 , wherein
the compression-ratio information indicates an entropy of each write data.
3. The memory system according to claim 2 , further comprising:
a volatile memory in which the compression ratio is stored in association with the entropy.
4. The memory system according to claim 1 , wherein
the compression-ratio information is indicated in a predetermined field of each write command.
5. The memory system according to claim 4 , wherein
the write commands conform to an NVMe standard.
6. The memory system according to claim 1 , wherein
the compression-ratio information is determined by a host that issues the write commands.
7. The memory system according to claim 1 , wherein
the controller acquires the write commands and the compression-ratio information from a relay device via the interface circuit.
8. The memory system according to claim 7 , wherein
the compression-ratio information is determined by the relay device.
9. The memory system according to claim 1 , wherein
the write commands include first, second, and third write commands issued in this order and associated with first, second, and third write data, respectively, and
upon receipt of the write commands and the first, second, and third write data, the controller determines the execution order of the write commands to be different from the issued order of the write commands if the first and second write data cannot be stored in a predetermined storage area and the first and third write data or the second and third write data can be stored in the predetermined storage area.
10. The memory system according to claim 9 , wherein
the controller comprises a buffer memory, and
the predetermined storage area is allocated in the buffer memory.
11. A memory system comprising:
a nonvolatile memory;
an interface circuit; and
a controller configured to
upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, compress the write data associated with each write command,
determine a data size of each compressed write data, and
determine an execution order of the write commands based on the determined data size.
12. The memory system according to claim 11 , further comprising:
a buffer memory in which the compressed write data is stored.
13. The memory system according to claim 11 , wherein
the controller is further configured to determine whether each write data can be compressed, and
the controller determines the data size only when the write data can be compressed.
14. The memory system according to claim 13 , wherein
the controller determines whether each write data can be compressed by referring to a predetermined field of the corresponding write command.
15. The memory system according to claim 14 , wherein
the write commands conform to an NVMe standard.
16. The memory system according to claim 11 , wherein
the write commands include first, second, and third write commands issued in this order and associated with first, second, and third write data, respectively, and
upon receipt of the write commands and the first, second, and third write data, the controller determines the execution order of the write commands to be different from the issued order of the write commands if the first and second write data cannot be stored in a predetermined storage area and the first and third write data or the second and third write data can be stored in the predetermined storage area.
17. The memory system according to claim 16 , wherein
the controller includes a buffer memory, and
the predetermined storage area is allocated in the buffer memory.
18. A memory system comprising:
a nonvolatile memory;
an interface circuit; and
a controller configured to
upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, determine whether the write data associated with each write command can be compressed by referring to a predetermined field of the write command,
compress each write data that can be compressed,
determine a data size of each compressed and uncompressed write data, and
determine an execution order of the write commands based on the determined data size.
19. The memory system according to claim 18 , wherein
the write commands conform to an NVMe standard.
20. The memory system according to claim 18 , wherein
the write commands include first, second, and third write commands issued in this order and associated with first, second, and third write data, respectively, and
upon receipt of the write commands and the first, second, and third write data, the controller determines the execution order of the write commands to be different from the issued order of the write commands if the first and second write data cannot be stored in a predetermined storage area and the first and third write data or the second and third write data can be stored in the predetermined storage area.