Memory system
According to one embodiment, a memory system is connectable to a host including a first volatile memory and includes a non-volatile memory and a controller. The controller may use a first area of the first volatile memory as a temporary storage memory of data stored in the non-volatile memory and controls the non-volatile memory. The controller generates a first parity by using first data stored in the non-volatile memory and a key value to store the first data and the generated first parity in the first area. In the case of reading the first data stored in the first area, the controller reads the first data and the first parity to verify the read first data using the read first parity and the key value.
1. A memory system connectable to a host that includes a first volatile memory, the system comprising:
a non-volatile memory; and
a controller configured to cause a first area of the first volatile memory to temporarily store data from the non-volatile memory and to generate a key value,
wherein the controller is further configured to:
generate a first parity using first data stored in the non-volatile memory and the generated key value;
cause the first data and the generated first parity to be stored in the first area; and
read the first data and the first parity stored in the first area to verify the read first data using the read first parity and the key value.
2. The memory system according to claim 1 , wherein
the controller is configured to generate a first key value as the key value in response to receiving, from the host, an instruction to enable the controller to use the first area.
3. The memory system according to claim 2 , wherein
after receiving, from the host, an instruction to disable the controller to use the first area, the controller is configured to generate a second key value different from the first key value as the key value in response to receiving, from the host, an instruction to enable the controller to use a second area of the first volatile memory.
4. The memory system according to claim 3 , wherein
the controller is configured to:
generate a second parity using second data stored in the second area and the second key value and cause the second parity to be stored in the second area; and
read the second data and the second parity, and then verify the read second data using the read second parity and the second key value.
5. The memory system according to claim 2 , wherein
in response to receiving, from the host, an instruction to disable the controller to use the first area, the controller is configured to use the first key value as the key value in response to receiving, from the host, an instruction to specify the first area and the data stored in the first area to be used continuously to enable the controller to use the first area.
6. The memory system according to claim 5 , wherein
the controller is configured to:
generate a third parity using third data stored in the first area and the first key value and cause the third parity to be stored in the first area; and
read the third data and the third parity, and then verify the read third data using the read third parity and the first key value.
7. The memory system according to claim 2 , wherein
the controller is configured to discard the first data when an error is determined in the read first data.
8. The memory system according to claim 4 , wherein
each of the first key value and the second key value includes a random number.
9. The memory system according to claim 2 , wherein
the first key value includes a random number.
10. The memory system according to claim 1 , further comprising:
a second volatile memory, wherein
the controller is configured to cause fourth data to be stored in the second volatile memory in response to determining that the fourth data read from the non-volatile memory is not to be stored in the first volatile memory.
11. The memory system according to claim 10 , wherein
the fourth data includes at least one of unencrypted user data, data of a security key used in the memory system, or data of firmware used in the memory system.
12. The memory system according to claim 2 , wherein
the instruction to enable the controller to use the first area conforms to a NVM Express standard.
13. The memory system according to claim 2 , wherein
the instruction to enable the controller to use the first area conforms to a UFS standard.
14. A method, comprising:
reading data from a non-volatile memory;
determining whether an instruction to enable a host volatile memory as a temporary storage area is received;
generating a key value;
generating, in response to receiving the instruction, a parity using the data stored in the non-volatile memory and the generated key value;
causing the data and the generated parity to be stored in an area of the host volatile memory; and
verifying the data using the parity and the key value in response to reading the data stored in the area of the host volatile memory.
15. The method of claim 14 , further comprising:
determining, in response to receiving the instruction, whether to store the data and the generated parity in the area of the host volatile memory based on at least one of: a type of the data, encryption of the data, or a security priority of the data.
16. The method of claim 14 , further comprising:
storing, in response to not receiving the instruction, the data in an internal volatile memory.