IP Library Granted Patent US 11,018,217
Granted Patent B2
US 11,018,217 · App. 16/549,826 · Granted May 25, 2021

Semiconductor device and method for manufacturing the same

Inventors: Takashi Ishida (Mie, JP); Takahiro Sugimoto (Mie, JP); Hiroshi Kanno (Mie, JP); Tatsuya Okamoto (Mie, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L29/04H01L21/823487H01L27/11556H01L27/11582
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Quick Facts
Patent No.
US 11,018,217
App. No.
16/549,826
Granted
May 25, 2021
Kind
B2
Abstract

A semiconductor device includes a first semiconductor layer that is an electrically-conductive polycrystalline semiconductor layer and a second semiconductor layer on the first semiconductor layer. The second semiconductor layer is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer. A plurality of electrode layers are stacked on the second semiconductor layer at intervals in a first direction. A third semiconductor layer extends in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacts the second semiconductor layer. A charge storage layer is between the plurality of electrode layers and the third semiconductor layer.

Claims (26)

1. A semiconductor device, comprising:

a first semiconductor layer which is an electrically-conductive polycrystalline semiconductor layer;

a second semiconductor layer on the first semiconductor layer and which is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer;

a plurality of electrode layers stacked on the second semiconductor layer at intervals in a first direction;

a third semiconductor layer extending in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacting the second semiconductor layer; and

a charge storage layer between the plurality of electrode layers and the third semiconductor layer, wherein

the second semiconductor layer includes a first region, which is a polycrystalline semiconductor layer having a first average grain size, and a second region, which is a polycrystalline semiconductor layer having a second average grain size which is larger than the first average grain size.

2. The semiconductor device according to claim 1 , wherein the average grain size of the first semiconductor layer is more than 100 nm, and the average grain size of the second semiconductor layer is less than 100 nm.

3. The semiconductor device according to claim 1 , wherein the first average grain size is less than 50 nm, and the second average grain size is more than 50 nm.

4. The semiconductor device according to claim 1 , wherein the first region is between the second region and the first semiconductor layer.

5. The semiconductor device according to claim 1 , wherein the second region is between the first region and the first semiconductor layer.

6. The semiconductor device according to claim 1 , wherein the first region is between the second region and the third semiconductor layer.

7. The semiconductor device according to claim 1 , wherein the first region is between an upper surface of the first semiconductor layer and a lower surface of the third semiconductor layer.

8. The semiconductor device according to claim 1 , wherein the first region includes impurity atoms other than boron atoms, phosphorus atoms, or arsenic atoms.

9. The semiconductor device according to claim 1 , wherein the first region includes carbon atoms or nitrogen atoms.

10. The semiconductor device according to claim 1 , wherein the concentration of impurity atoms in the first region is more than 1.4×10 21 /cm 3 .

11. A semiconductor device, comprising:

a first semiconductor layer;

a second semiconductor layer on the first semiconductor layer and including impurity atoms other than boron atoms, phosphorus atoms, or arsenic atoms;

a plurality of electrode layers stacked on the second semiconductor layer at intervals in a first direction;

a third semiconductor layer extending in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers, and contacting the second semiconductor layer; and

a charge storage layer between the plurality of electrode layers and the third semiconductor layer, wherein

the second semiconductor layer includes a first region whose concentration of the impurity atoms is more than 1.4×10 21 /cm 3 and a second region whose concentration of the impurity atoms is less than 1.4×10 21 /cm 3 .

12. The semiconductor device according to claim 11 , wherein

the first region is a polycrystalline semiconductor region having a first average grain size, and

the second region is a polycrystalline semiconductor region having a second average grain size that is larger than the first average grain size.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2019
From: ISHIDA, TAKASHI; SUGIMOTO, TAKAHIRO; KANNO, HIROSHI; OKAMOTO, TATSUYA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051249/0424 →