GaN circuit drivers for GaN circuit loads
An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.
1. An electronic circuit, comprising:
a semiconductor substrate;
a first power supply node on the semiconductor substrate;
an output node;
a signal node;
a pull-up switch on the semiconductor substrate, wherein the pull-up switch is configured to selectively conduct current from the first power supply node to the output node based at least in part on a voltage at the signal node;
a charging element; and
a capacitor coupled to the output node, wherein the charging element is configured to selectively conduct current to the capacitor to increase a capacitor voltage across the capacitor, wherein the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the pull-up switch causes the voltage at the output node to be substantially equal to the voltage of the first power supply node, and wherein the charging element is substantially non-conductive while the voltage at the signal node is greater than the voltage of the first power supply node.
2. The electronic circuit of claim 1 , wherein the semiconductor substrate comprises GaN and the pull-up switch comprises a GaN transistor.
3. The electronic circuit of claim 1 , wherein the charging element is configured to conduct current to the capacitor while the capacitor does not cause the voltage at the signal node to be greater than the voltage of the first power supply node.
4. The electronic circuit of claim 1 , wherein the capacitor causes the voltage at the signal node to be greater than the voltage of the first power supply node in response to the voltage at the output node increasing.
5. The electronic circuit of claim 1 , further comprising a resistive element connected to the capacitor and to the pull-up switch.
6. The electronic circuit of claim 1 , further comprising a pull-down device coupled to the signal node, wherein the pull-down device is configured to conduct current from the signal node.
7. The electronic circuit of claim 1 , further comprising:
an input node; and
a feedback element connected to the input node and to the output node,
wherein the voltage generated at the output node is based at least in part on an input voltage at the input node, and wherein a relationship between the voltage at the input node and the voltage at the output node is hysteretic.
8. The electronic circuit of claim 1 , further comprising a power switch formed on the semiconductor substrate, wherein the power switch includes a control gate coupled to the output node.
9. The electronic circuit of claim 1 , wherein the electronic circuit comprises two inverters connected serially to form a non-inverting buffer circuit.
10. The electronic circuit of claim 1 , further comprising an input node, wherein the voltage generated at the output node is a logic inversion of the input node.
11. A method of operating an electronic circuit, the electronic circuit comprising:
a semiconductor substrate,
a first power supply node on the semiconductor substrate,
an output node,
a signal node,
a pull-up switch on the semiconductor substrate,
a charging element, and
a capacitor coupled to the output node,
the method comprising:
with the pull-up switch, selectively conducting current from the first power supply node to the output node based at least in part on a voltage at the signal node;
with the charging element, selectively conducting current to the capacitor to increase a capacitor voltage across the capacitor; and
with the capacitor, selectively causing the voltage at the signal node to be greater than the voltage of the first power supply node, such that the pull-up switch causes the voltage at the output node to be substantially equal to the voltage of the first power supply node, and wherein the charging element is substantially non-conductive while the voltage at the signal node is greater than the voltage of the first power supply node.
12. The method of claim 11 , wherein the semiconductor substrate comprises GaN and the pull-up switch comprises a GaN transistor.
13. The method of claim 11 , further comprising, with the charging element, conducting current to the capacitor while the capacitor does not cause the voltage at the signal node to be greater than the voltage of the first power supply node.
14. The method of claim 11 , further comprising, with the capacitor, causing the voltage at the signal node to be greater than the voltage of the first power supply node in response to the voltage at the output node increasing.
15. The method of claim 11 , further comprising, with the capacitor, causing the voltage at the signal node to be greater than the voltage of the first power supply node by sourcing current to the signal node through a resistive element.
16. The method of claim 11 , wherein the electronic circuit further comprises a pull-down device coupled to the signal node, the method further comprising, with the pull-down device conducting current from the signal node.
17. The method of claim 11 , wherein the electronic circuit further comprises:
an input node, and
a feedback element between the input node and the output node,
wherein the voltage generated at the output node is based at least in part on an input voltage at the input node, and wherein a relationship between the voltage at the input node and the voltage at the output node is hysteretic.
18. The method of claim 11 , wherein the electronic circuit further comprises a power switch formed on the semiconductor substrate including a control gate coupled to the output node, wherein the method further comprises controlling a conductivity state of the power switch with the voltage at the output node.
19. The method of claim 11 , wherein the electronic circuit further comprises two inverters connected serially to form a non-inverting buffer circuit.
20. The method of claim 11 , wherein the electronic circuit further comprises an input node, wherein the voltage generated at the output node is a logic inversion of the input node.