IP Library Granted Patent US 11,107,987
Granted Patent B2
US 11,107,987 · App. 16/551,259 · Granted Aug 31, 2021

Semiconductor storage device

Inventor: Hironobu Furuhashi (Kuwana Mie, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L45/144G11C13/004G11C13/0004G11C13/0069H01L27/2409H01L27/2481H01L27/2436H01L45/06H01L45/1233
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Quick Facts
Patent No.
US 11,107,987
App. No.
16/551,259
Granted
Aug 31, 2021
Kind
B2
Abstract

A semiconductor storage device includes a first conductive layer, a second conductive layer, and a first chalcogen layer provided therebetween. A third conductive layer and a fourth conductive layer have a second chalcogen layer provided therebetween. The second chalcogen layer contains tellurium (Te). When a minimum value and a maximum value of a composition ratio of tellurium in the second chalcogen layer observed along the first direction are a first minimum value and a first maximum value, respectively, the first minimum value is observed at a position closer to the third conductive layer than a center position in the first direction of the second chalcogen layer, and the first maximum value is observed at a position closer to the fourth conductive layer than the center position in the first direction of the second chalcogen layer.

Claims (75)

1. A semiconductor storage device, comprising:

a first conductive layer, a second conductive layer separated from the first conductive layer in a first direction, and a first chalcogen layer provided between the first conductive layer and the second conductive layer;

a third conductive layer, a fourth conductive layer separated from the third conductive layer in the first direction, and a second chalcogen layer provided between the third conductive layer and the fourth conductive layer; and

a peripheral circuit connected to the first conductive layer and the second conductive layer, wherein

the third conductive layer and the fourth conductive layer are not connected to the peripheral circuit,

the second chalcogen layer contains tellurium (Te), and

when a minimum value and a maximum value of a composition ratio of tellurium in the second chalcogen layer observed along the first direction are a first minimum value and a first maximum value, respectively,

the first minimum value is observed at a position closer to the third conductive layer than a center position in the first direction of the second chalcogen layer, and

the first maximum value is observed at a position closer to the fourth conductive layer than the center position in the first direction of the second chalcogen layer.

2. The semiconductor storage device according to claim 1 , wherein

the first chalcogen layer contains tellurium, and

when a minimum value and a maximum value of a composition ratio of tellurium in the first chalcogen layer observed along the first direction are a second minimum value and a second maximum value, respectively,

a difference between the second maximum value and the second minimum value is smaller than a difference between the first maximum value and the first minimum value.

3. The semiconductor storage device according to claim 2 , wherein

the first chalcogen layer and the second chalcogen layer each contain germanium (Ge), antimony (Sb), and tellurium (Te).

4. The semiconductor storage device according to claim 2 , wherein

the first conductive layer and the third conductive layer are provided in a same wiring layer,

the second conductive layer and the fourth conductive layer are provided in a same wiring layer, and

in at least one of a write operation or a read operation, a voltage of the first conductive layer is greater than a voltage of the second conductive layer.

5. The semiconductor storage device according to claim 2 , wherein

the first conductive layer and the third conductive layer are provided in a same wiring layer,

the second conductive layer and the fourth conductive layer are provided in a same wiring layer, and

the first chalcogen layer includes an amorphous region provided between the first conductive layer and the second conductive layer, and a crystalline region provided between the amorphous region and the second conductive layer.

6. The semiconductor storage device according to claim 1 , wherein

the first chalcogen layer and the second chalcogen layer each contain germanium (Ge), antimony (Sb), and tellurium (Te).

7. The semiconductor storage device according to claim 6 , wherein

the first conductive layer and the third conductive layer are provided in a same wiring layer,

the second conductive layer and the fourth conductive layer are provided in a same wiring layer, and

in at least one of a write operation or a read operation, a voltage of the first conductive layer is greater than a voltage of the second conductive layer.

8. The semiconductor storage device according to claim 6 , wherein

the first conductive layer and the third conductive layer are provided in a same wiring layer,

the second conductive layer and the fourth conductive layer are provided in a same wiring layer, and

the first chalcogen layer includes an amorphous region provided between the first conductive layer and the second conductive layer, and a crystalline region provided between the amorphous region and the second conductive layer.

9. The semiconductor storage device according to claim 1 , wherein

the first conductive layer and the third conductive layer are provided in a same wiring layer,

the second conductive layer and the fourth conductive layer are provided in a same wiring layer, and

in at least one of a write operation or a read operation, a voltage of the first conductive layer is greater than a voltage of the second conductive layer.

10. The semiconductor storage device according to claim 1 , wherein

the first conductive layer and the third conductive layer are provided in a same wiring layer,

the second conductive layer and the fourth conductive layer are provided in a same wiring layer, and

the first chalcogen layer includes an amorphous region provided between the first conductive layer and the second conductive layer, and a crystalline region provided between the amorphous region and the second conductive layer.

11. The semiconductor storage device according to claim 1 , wherein the first chalcogen layer is a resistance-variable element.

12. A semiconductor storage device, comprising:

a first conductive layer, a second conductive layer separated from the first conductive layer in a first direction, and a first chalcogen layer provided between the first conductive layer and the second conductive layer;

a third conductive layer, a fourth conductive layer separated from the third conductive layer in the first direction, and a second chalcogen layer provided between the third conductive layer and the fourth conductive layer; and

a peripheral circuit connected to the first conductive layer and the second conductive layer, wherein

the third conductive layer and the fourth conductive layer are not connected to the peripheral circuit,

the second chalcogen layer contains antimony (Sb), and

when a minimum value and a maximum value of a composition ratio of antimony in the second chalcogen layer observed along the first direction are a third minimum value and a third maximum value, respectively,

the third minimum value is observed at a position closer to the fourth conductive layer than a center position in the first direction of the second chalcogen layer, and

the third maximum value is observed at a position closer to the third conductive layer than the center position in the first direction of the second chalcogen layer.

13. The semiconductor storage device according to claim 12 , wherein

the first chalcogen layer contains antimony, and

when a minimum value and a maximum value of a composition ratio of antimony in the first chalcogen layer observed along the first direction are a fourth minimum value and a fourth maximum value, respectively,

a difference between the fourth maximum value and the fourth minimum value is smaller than a difference between the third maximum value and the third minimum value.

14. The semiconductor storage device according to claim 13 , wherein

the first chalcogen layer and the second chalcogen layer each contain germanium (Ge), antimony (Sb), and tellurium (Te).

15. The semiconductor storage device according to claim 13 , wherein

the first conductive layer and the third conductive layer are provided in a same wiring layer,

the second conductive layer and the fourth conductive layer are provided in a same wiring layer, and

in at least one of a write operation or a read operation, a voltage of the first conductive layer is greater than a voltage of the second conductive layer.

16. The semiconductor storage device according to claim 13 , wherein

the first conductive layer and the third conductive layer are provided in a same wiring layer,

the second conductive layer and the fourth conductive layer are provided in a same wiring layer, and

the first chalcogen layer includes an amorphous region provided between the first conductive layer and the second conductive layer, and a crystalline region provided between the amorphous region and the second conductive layer.

17. The semiconductor storage device according to claim 12 , wherein

the first chalcogen layer and the second chalcogen layer each contain germanium (Ge), antimony (Sb), and tellurium (Te).

18. The semiconductor storage device according to claim 12 , wherein

the first conductive layer and the third conductive layer are provided in a same wiring layer,

the second conductive layer and the fourth conductive layer are provided in a same wiring layer, and

in at least one of a write operation or a read operation, a voltage of the first conductive layer is greater than a voltage of the second conductive layer.

19. The semiconductor storage device according to claim 12 , wherein

the first conductive layer and the third conductive layer are provided in a same wiring layer,

the second conductive layer and the fourth conductive layer are provided in a same wiring layer, and

the first chalcogen layer includes an amorphous region provided between the first conductive layer and the second conductive layer, and a crystalline region provided between the amorphous region and the second conductive layer.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2020
From: FURUHASHI, HIRONOBU
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051673/0700 →
Priority Claims (1)
JP JP2019-030962 · Feb 22, 2019 · national
Continuity (1)
Related Publication 20200274063A1 · Aug 27, 2020