IP Library Patent Application 16551421
Patent Application
App. No. 16/551,421

INTEGRATED SYSTEM OF PDN IMPLEMENTATION AND DIGITAL CO-SYNTHESIS

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Quick Facts
Patent No.
US None
App. No.
16/551,421
Abstract

Design of a power delivery network (PDN) is integrated with a digital logic design flow.

Claims (14)

1 . A method useful in integrated circuit design, comprising:

receiving, by a computer, design parameters for a power delivery network (PDN) to be instantiated in an integrated circuit chip (IC);

receiving, by the computer, a model of logic circuitry for an integrated circuit;

simulating operation of a plurality of configurations of the PDN for the model of logic circuitry over a specified range of minimum voltages to indicate at least a best-for-area PDN configuration or a best-for-power PDN configuration of the plurality of configurations of the PDN;

generating, using the computer, a netlist of PDN components and interconnects for a selected PDN configuration, the selected PDN configuration being the best-for-area PDN configuration or the best-for-power PDN configuration;

instantiating the generated netlist into RTL models of a combined digital circuit design for the logic circuitry and selected PDN configuration; and

synthesizing the combined digital circuit design.

2 .- 4 . (canceled)

5 . The method of claim 1 , wherein the parameters for the PDN comprise voltage regulator (VR) error, VR efficiency, and VR area.

6 . The method of claim 5 , wherein the parameters for the PDN further comprise bump properties and on-die metal capacitor capacitance and area.

7 . The method of claim 1 , wherein the model of logic circuitry comprises a model of area and current for the logic circuitry.

8 . The method of claim 1 , wherein the netlist representation includes information regarding a number of bumps for the PDN.

9 . The method of claim 1 , wherein the parameters for the PDN comprise automatic transient control (ATC) circuit area.

10 . The method of claim 9 , wherein the netlist includes information regarding a number of embedded voltage regulators and a number of ATC circuits.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2023
From: CHAOYANG SEMICONDUCTOR (SHANGHAI) CO., LTD.
To: ENDURA IP HOLDINGS LTD.
Reel/Frame 063424/0226 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2019
From: DOSLUOGLU, TANER; GELMAN, ANATOLY
To: ENDURA TECHNOLOGIES LLC
Reel/Frame 050795/0591 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2019
From: ENDURA TECHNOLOGIES LLC
To: ENDURA IP HOLDINGS LTD.
Reel/Frame 050795/0616 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2019
From: ENDURTECH (HONG KONG) LIMITED
To: CHAOYANG SEMICONDUCTOR JIANGYIN TECHNOLOGY CO., LTD.
Reel/Frame 050795/0632 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2019
From: ENDURA IP HOLDINGS LTD.
To: ENDURTECH (HONG KONG) LIMITED
Reel/Frame 050797/0348 →