VERTICAL SEMICONDUCTOR DEVICE WITH THINNED SUBSTRATE
A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.
1 . A device comprising:
a gate region;
an active region having source, drain, and channel regions arranged as a vertical power device, at least a portion of a substrate material below the active region having been removed to isolate the active region and to expose the drain and channel regions; and
at least one bottom side electrode connected to at least one of the exposed drain and channel regions;
and wherein:
the drain region is located below the gate region;
the channel region isolates the drain region from the source region;
the channel region has a bottom boundary and a side boundary;
the side boundary extends downward from below the gate region to the bottom boundary; and
the drain and channel regions are in contact along the side boundary and are not in contact along the bottom boundary, wherein:
the source region has a second bottom boundary and a second side boundary;
the second side boundary extends downward from a top surface of the active region to the second bottom boundary; and
the source and channel regions are in contact along the second side boundary and are not in contact along the second bottom boundary.
2 . The device of claim 1 , further comprising:
a trench region extending along an entire vertical side of the active region and horizontally surrounding the active region to electrically isolate the active region within an integrated circuit chip.
3 . The device of claim 2 , wherein:
the vertical power device is contained within a first region of the integrated circuit chip;
the first region of the integrated circuit chip has a first thickness;
a second region of the integrated circuit chip has a second thickness smaller than the first thickness and contains at least one non-vertical semiconductor device; and
the trench region electrically isolates the first and second regions from each other.
4 . The device of claim 2 , wherein the portion of the substrate material below the active region has been removed up to both the active region and the trench region.
5 . The device of claim 1 , wherein the portion of the substrate material below the active region has been removed to expose the source region.
6 . The device of claim 1 , further comprising;
a first bottom side electrode connected to the drain region;
a second bottom side electrode connected to the source region; and
a third bottom side electrode coupled to the gate region.
7 . The device of claim 1 , further comprising a handle wafer bonded above the active region.
8 . A device comprising:
a gate region;
an active region having source, drain, and channel regions arranged as a vertical power device, a portion of a substrate material below the active region having been removed to expose the drain and channel regions; and
a first bottom side electrode connected to a drain region;
and wherein:
the channel region isolates the drain region from the source region;
the channel region has a bottom boundary and a side boundary;
the side boundary extends downward from below the gate region to the bottom boundary; and
the drain and channel regions are in contact along the side boundary and are not in contact along the bottom boundary, wherein:
the source region has a second bottom boundary and a second side boundary;
the second side boundary extends downward from a top surface of the active region to the second bottom boundary; and
the source and channel regions are in contact along the second side boundary and are not in contact along the second bottom boundary.
9 . The device of claim 8 , further comprising:
a trench region extending along a vertical side of the active region and horizontally surrounding the active region to electrically isolate the active region within an integrated circuit chip.
10 . The device of claim 9 , wherein:
the vertical power device is contained within a first region of the integrated circuit chip;
the first region of the integrated circuit chip has a first thickness;
a second region of the integrated circuit chip has a second thickness smaller than the first thickness and contains at least one non-vertical semiconductor device; and
the trench region electrically isolates the first and second regions from each other.
11 . The device of claim 9 , wherein the portion of the substrate material below the active region has been removed up to both the active region and the trench region.
12 . The device of claim 8 , wherein the portion of the substrate material below the active region has been removed to expose the source region.
13 . The device of claim 8 , further comprising;
a second bottom side electrode connected to the source region; and
a third bottom side electrode coupled to the gate region.
14 . The device of claim 8 , further comprising a handle wafer bonded above the active region.
15 . A vertical power device comprising:
an active semiconductor region having a plurality of fabricated semiconductor structures comprising a source, drain and channel, the active semiconductor region being exposed on a bottom side; and
a first bottom side electrode connected to the drain, wherein:
the channel isolates the source from the drain;
the channel has a bottom boundary and a side boundary extending downward from a top surface of the active semiconductor region to the bottom boundary;
the drain and channel are in contact along the side boundary and are not in contact along the bottom boundary;
the source has a second bottom boundary and a second side boundary extending downward from the top surface of the active semiconductor region to the second bottom boundary; and
the source and the channel are in contact along the second side boundary and are not in contact along the second bottom boundary.
16 . The vertical power device of claim 15 , further comprising:
a handle wafer layer bonded above the active semiconductor region.
17 . The vertical power device of claim 15 , further comprising:
a trench region extending along a vertical side of the active semiconductor region and horizontally surrounding the active semiconductor region;
wherein the trench region electrically isolates the vertical semiconductor device from a second active semiconductor region on an integrated circuit chip.
18 . The vertical power device of claim 17 , wherein:
the vertical semiconductor device is contained within a first region of the integrated circuit chip;
the first region of the integrated circuit chip has a first thickness; and
a second region of the integrated circuit chip has a second thickness that is smaller than the first thickness, and the second region contains at least one non-vertical semiconductor device.
19 . The vertical power device of claim 15 , wherein a portion of substrate material below the active region has been removed to expose the source.
20 . The vertical power device of claim 15 , further comprising;
a second bottom side electrode connected to the source; and
a third bottom side electrode coupled to a gate.