IP Library Granted Patent US 11,461,039
Granted Patent B2
US 11,461,039 · App. 16/554,381 · Granted Oct 4, 2022

Nonvolatile memory that stores temperature information therein

Inventor: Yasuhiko Kurosawa (Fujisawa Kanagawa, JP)
Assignee: KIOXIA CORPORATION
G06F3/0655G06F3/0604G06F3/0679G06K19/0717
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Quick Facts
Patent No.
US 11,461,039
App. No.
16/554,381
Granted
Oct 4, 2022
Kind
B2
Abstract

A nonvolatile memory includes a memory array, a sensor for measuring a temperature, an interface through which a write command is to be received, and a control circuit. The control circuit is configured to write information of the temperature measured by the sensor in a data storing area of the memory array in which user data associated with the write command is not capable of being written into, when writing the user data in the memory array in response to the received write command.

Claims (15)

1. A nonvolatile memory comprising:

a memory array having a plurality of memory cells including a first set and a second set, wherein the memory cells of the first set and the memory cells of the second set are connected to a common word line;

a sensor for measuring a temperature;

an interface through which a write command is to be received; and

a control circuit configured to write user data, parity data, and temperature information in response to the write command, wherein

in response to a write command designating the common word line, the control circuit writes the user data and the parity data in the first set of the plurality of memory cells connected to the common word line and the temperature information in the second set of the plurality of memory cells connected to the common word line, the temperature information being acquired from the sensor and corresponding to the temperature measured by the sensor when the control circuit is writing the user data and the parity data, and

the user data and the parity data are written in the first set of the plurality of memory cells according to a first writing mode and the temperature information is written in the second set of the plurality of memory cells according to a second writing mode, wherein the first writing mode and the second writing mode are different.

2. The nonvolatile memory according to claim 1 , wherein the temperature information is stored in a dedicated area in the memory array that includes the second set of the plurality of memory cells.

3. The nonvolatile memory according to claim 2 , wherein

upon receiving a command including designation of the dedicated area through the interface, the control circuit reads the temperature information written in the dedicated area in response to the command, and outputs the temperature information via the interface.

4. The nonvolatile memory according to claim 1 , wherein the temperature information is stored in a redundant region in the memory array that includes the second set of the plurality of memory cells.

5. The nonvolatile memory according to claim 4 , wherein

upon receiving a command including designation of the redundant region through the interface, the control circuit reads the temperature information written in the redundant region in response to the command, and outputs the temperature information via the interface.

6. The nonvolatile memory according to claim 1 , wherein the first writing mode is a writing mode by which more than one bit are written per memory cell and the second writing mode is a writing mode by which only one bit is written per memory cell.

7. The nonvolatile memory according to claim 1 , wherein the memory array includes a plurality of blocks and one of the blocks includes the memory cells of the first set and the memory cells of the second set.

Assignments (2)
CHANGE OF NAME Recorded Jan 13, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058777/0822 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2019
From: KUROSAWA, YASUHIKO
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 050765/0415 →