IP Library Granted Patent US 11,101,279
Granted Patent B2
US 11,101,279 · App. 16/554,861 · Granted Aug 24, 2021

Semiconductor memory device

Inventors: Ken Komiya (Nagoya, JP); Takamasa Ito (Nagoya, JP); Naoki Yamamoto (Kuwana, JP); Yu Hirotsu (Kuwana, JP); Kazuhiro Tomishige (Yokkaichi, JP); Yoshinori Nakakubo (Yokkaichi, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11556H01L23/53295H01L27/11519H01L27/11565H01L27/11582H01L21/0217H01L21/02211H01L21/02271H01L21/31111
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Quick Facts
Patent No.
US 11,101,279
App. No.
16/554,861
Granted
Aug 24, 2021
Kind
B2
Abstract

A semiconductor memory device includes: a substrate including a first and a second regions; first wiring layers disposed in a first direction; a second wiring layer; a third wiring layer closer to the substrate than the first and the second wiring layers; a semiconductor film that penetrates the first and the second wiring layers, and is connected to the third wiring layer; and a gate insulating film disposed between the semiconductor film and the first wiring layers. The first wiring layers include first conductive films opposed to the semiconductor film in the first region, and first films in the second region. The second wiring layer includes a second conductive film opposed to the semiconductor film in the first region, and a second film in the second region. The second film is different from the first films.

Claims (36)

1. A semiconductor memory device, comprising:

a substrate that includes a first region and a second region;

a plurality of first wiring layers disposed in a first direction intersecting with a surface of the substrate;

a second wiring layer having a distance from the substrate different from distances of the plurality of the first wiring layers from the substrate;

a third wiring layer close to the substrate with respect to the plurality of the first wiring layers and the second wiring layer;

a semiconductor film that penetrates the plurality of the first wiring layers and the second wiring layer, extends in the first direction, and is connected to the third wiring layer; and

a gate insulating film disposed between the semiconductor film and the plurality of the first wiring layers, wherein

the plurality of the first wiring layers include first conductive films opposed to the semiconductor film in the first region, and the plurality of the first wiring layers include first films different from the first conductive films in the second region,

the second wiring layer includes a second conductive film opposed to the semiconductor film in the first region, and the second wiring layer includes a second film different from the second conductive film in the second region,

the second film is different from the first films, and

the second film has at least one of:

a density larger than densities of the first films;

a content rate of hydrogen smaller than content rates of hydrogen of the first films; and

an etching rate of a first chemical solution smaller than etching rates of the first chemical solution of the first films.

2. The semiconductor memory device according to claim 1 , further comprising

an interlayer insulating film disposed between the plurality of the first wiring layers, wherein

the interlayer insulating film has:

an etching rate of the first chemical solution smaller than the etching rate of the first chemical solution of the second film; and

an etching rate of a second chemical solution larger than an etching rate of the second chemical solution of the second film.

3. The semiconductor memory device according to claim 1 , wherein

the second wiring layer further includes one of the first films in the second region.

4. The semiconductor memory device according to claim 1 , wherein

the first films and the second film contain nitrogen.

5. The semiconductor memory device according to claim 1 , wherein

the second wiring layer is close to the substrate with respect to the plurality of the first wiring layers.

6. The semiconductor memory device according to claim 1 , wherein

the second wiring layer is far from the substrate with respect to the plurality of the first wiring layers.

7. The semiconductor memory device according to claim 1 , wherein

the semiconductor film includes a first part where a width in a second direction intersecting with the first direction becomes a maximum or a local maximum, and

the first part of the semiconductor film is opposed to the second conductive film or an interlayer insulating film adjacent to the second conductive film in the first direction.

8. The semiconductor memory device according to claim 1 , further comprising

a plurality of the second wiring layer disposed in the first direction.

9. The semiconductor memory device according to claim 8 , wherein

the plurality of the second wiring layer includes a plurality of the second films, and thicknesses in the first direction of the plurality of the second films are different from each other.

10. The semiconductor memory device according to claim 1 , wherein

the third wiring layer includes a laminated film having a conductive property.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2019
From: KOMIYA, KEN; ITO, TAKAMASA; YAMAMOTO, NAOKI; HIROTSU, YU; TOMISHIGE, KAZUHIRO; NAKAKUBO, YOSHINORI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 050430/0677 →
Priority Claims (1)
JP JP2018-166581 · Sep 6, 2018 · national
Continuity (1)
Related Publication 20200083239A1 · Mar 12, 2020
Cited By (1)
US 12,506,010