Constant current circuit for suppressing transient variation in constant current
View Patent ↗A constant current circuit includes a first current mirror circuit connected to a first power supply and having a first input transistor and a first output transistor of a first conductivity type, a second current mirror circuit having a second output transistor of a second conductivity type provided between the first input transistor and a second power supply, and a second input transistor of the second conductivity type provided between the first output transistor and the second power supply, a resistor interposed between the second output transistor and the second power supply, and a capacitor having one end connected to the first power supply and the other end connected to a connecting point of the second output transistor and the resistor.
1. A constant current circuit, comprising:
a first current mirror circuit connected to a first power supply and having a first input transistor and a first output transistor of a first conductivity type;
a second current mirror circuit having a second output transistor of a second conductivity type provided between the first input transistor and a second power supply, and a second input transistor of the second conductivity type provided between the first output transistor and the second power supply;
a resistor interposed between the second output transistor and the second power supply; and
a capacitor having one end connected to the first power supply and the other end connected to a connecting point of the second output transistor and the resistor, wherein the capacitor is configured to cancel voltage fluctuations.
2. The constant current circuit according to claim 1 , further comprising a third transistor of the first conductivity type interposed between the first power supply and the one end of the capacitor and having a gate connected to a gate and a drain of the first input transistor.
3. The constant current circuit according to claim 2 , further comprising a delay element configured to delay an on state of the third transistor.