IP Library Granted Patent US 11,314,868
Granted Patent B2
US 11,314,868 · App. 16/556,439 · Granted Apr 26, 2022

Rapidly establishing a chain of trust in a computing system

Inventors: Yvonne Hou (Fremont, CA); Sunil Mekad (Bangalore, IN); Prathap Sirishe (Milpitas, CA); Satish D Deo (Cupertino, CA); Umar Badusha (Bangalore, IN)
Assignee: Fungible, Inc.
G06F21/575G06F11/1417G06F11/1441H04L9/3252
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Quick Facts
Patent No.
US 11,314,868
App. No.
16/556,439
Granted
Apr 26, 2022
Kind
B2
Abstract

A system root of trust device of a computing system authenticates boot images associated with data processing units of the computing system. The device includes at least one processor configured to determine whether a first set of boot code associated with a first processor of the computing system is authentic, in response to determining that the first set of boot code is authentic, reset the first processor to allow the first processor to boot and authenticate first executable code to be executed by the first processor, after resetting the first processor, determine whether a second set of boot code associated with a second processor of the computing system is authentic, and in response to determining that the second set of boot code is authentic, reset the second processor to allow the second processor to boot and to authenticate second executable code to be executed by the second processor.

Claims (61)

1. A method comprising:

determining, by a system root of trust device of a computing system, whether a first set of boot code associated with a first processor of the computing system is authentic;

in response to determining that the first set of boot code is authentic, resetting, by the system root of trust device, the first processor to allow the first processor to boot and to authenticate one or more sets of first executable code to be executed by the first processor;

after resetting the first processor, determining, by the system root of trust device, whether a second set of boot code associated with a second processor of the computing system is authentic in parallel with the first processor authenticating the one or more sets of first executable code; and

in response to determining that the second set of boot code is authentic, resetting, by the system root of trust device, the second processor to allow the second processor to boot and to authenticate one or more sets of second executable code to be executed by the second processor.

2. The method of claim 1 , further comprising:

determining, by the first processor, whether the one or more sets of first executable code are authentic; and

determining, by the second processor, whether the one or more sets of second executable code are authentic.

3. The method of claim 1 , further comprising:

after completing a boot cycle of the computing system, determining that the first processor has failed; and

in response to determining that the first processor has failed, resetting the first processor without resetting the second processor.

4. The method of claim 1 ,

wherein determining whether the first set of boot code is authentic comprises accessing the first set of boot code via a multiplexer, and

wherein determining whether the second set of boot code is authentic comprises accessing the second set of boot code via the multiplexer.

5. The method of claim 4 ,

wherein accessing the first set of boot code comprises accessing the first set of boot code on a first flash device without copying the first set of boot code, and

wherein accessing the second set of boot code comprises accessing the second set of boot code on a second flash device without copying the second set of boot code.

6. The method of claim 1 ,

wherein determining whether the first set of boot code is authentic comprises executing elliptic curve digital signature algorithm (ECDSA) with the first set of boot code, and

wherein determining whether the second set of boot code is authentic comprises executing the ECDSA with the second set of boot code.

7. A system root of trust device of a computing system, the system root of trust device comprising one or more processors implemented in circuitry and configured to:

determine whether a first set of boot code associated with a first processor of the computing system is authentic;

in response to determining that the first set of boot code is authentic, reset the first processor to allow the first processor to boot and to authenticate one or more sets of first executable code to be executed by the first processor;

after resetting the first processor, determine whether a second set of boot code associated with a second processor of the computing system is authentic in parallel with the first processor authenticating the one or more sets of first executable code; and

in response to determining that the second set of boot code is authentic, reset the second processor to allow the second processor to boot and to authenticate one or more sets of second executable code to be executed by the second processor.

8. The system root of trust device of claim 7 , wherein the one or more processors are further configured to:

after completing a boot cycle of the computing system, determine that the first processor has failed; and

in response to determining that the first processor has failed, reset the first processor without resetting the second processor.

9. The system root of trust device of claim 7 ,

wherein to determine whether the first set of boot code is authentic, the one or more processors are configured to access the first set of boot code via a multiplexer, and

wherein to determine whether the second set of boot code is authentic, the one or more processors are configured to access the second set of boot code via the multiplexer.

10. The system root of trust device of claim 9 ,

wherein the one or more processors are configured to access the first set of boot code on a first flash device without copying the first set of boot code, and

wherein the one or more processors are configured to access the second set of boot code on a second flash device without copying the second set of boot code.

11. The system root of trust device of claim 7 ,

wherein to determine whether the first set of boot code is authentic, the one or more processors are configured to execute an elliptic curve digital signature algorithm (ECDSA) with the first set of boot code, and

wherein to determine whether the second set of boot code is authentic, the one or more processors are configured to execute the ECDSA with the second set of boot code.

12. A computing system comprising:

a plurality of processors including a first processor and a second processor; and

a system root of trust device comprising one or more processors implemented in circuitry and configured to:

determine whether a first set of boot code associated with a first processor of the computing system is authentic;

in response to determining that the first set of boot code is authentic, reset the first processor to allow the first processor to boot and to authenticate one or more sets of first executable code to be executed by the first processor;

after resetting the first processor, determine whether a second set of boot code associated with a second processor of the computing system is authentic in parallel with the first processor authenticating the one or more sets of first executable code; and

in response to determining that the second set of boot code is authentic, reset the second processor to allow the second processor to boot and to authenticate one or more sets of second executable code to be executed by the second processor.

13. The computing system of claim 12 ,

wherein the first processor is configured to determine whether the one or more sets of first executable code are authentic, and

wherein the second processor is configured to determine whether the one or more sets of second executable code are authentic.

14. The computing system of claim 12 , wherein the one or more processors are further configured to:

after completing a boot cycle of the computing system, determine that the first processor has failed; and

in response to determining that the first processor has failed, reset the first processor without resetting the second processor.

15. The computing system of claim 12 , further comprising a multiplexor,

wherein to determine whether the first set of boot code is authentic, the one or more processors are configured to access the first set of boot code via the multiplexer, and

wherein to determine whether the second set of boot code is authentic, the one or more processors are configured to access the second set of boot code via the multiplexer.

16. The computing system of claim 15 , further comprising a first flash device storing the first set of boot code and a second flash device storing the second set of boot code,

wherein the one or more processors are configured to access the first set of boot code on the first flash device without copying the first set of boot code, and

wherein the one or more processors are configured to access the second set of boot code on the second flash device without copying the second set of boot code.

17. A computer-readable storage medium having stored thereon instructions that, when executed, cause a processor of a system root of trust device of a computing system to:

determine whether a first set of boot code associated with a first processor of the computing system is authentic;

in response to determining that the first set of boot code is authentic, reset the first processor to allow the first processor to boot and to authenticate one or more sets of first executable code to be executed by the first processor;

after resetting the first processor, determine whether a second set of boot code associated with a second processor of the computing system is authentic in parallel with the first processor authenticating the one or more sets of first executable code; and

in response to determining that the second set of boot code is authentic, reset the second processor to allow the second processor to boot and to authenticate one or more sets of second executable code to be executed by the second processor.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2023
From: FUNGIBLE, INC.
To: MICROSOFT TECHNOLOGY LICENSING, LLC
Reel/Frame 064434/0430 →
RELEASE OF SECURITY INTEREST Recorded Jan 9, 2023
From: HERCULES CAPITAL, INC., AS AGENT
To: FUNGIBLE, INC.
Reel/Frame 062335/0803 →
RELEASE OF SECURITY INTEREST Recorded Jan 5, 2023
From: SILICON VALLEY BANK
To: FUNGIBLE, INC.
Reel/Frame 062308/0191 →
SECURITY INTEREST Recorded Dec 16, 2021
From: FUNGIBLE, INC.
To: SILICON VALLEY BANK
Reel/Frame 058523/0960 →
SECURITY INTEREST Recorded Dec 16, 2021
From: FUNGIBLE, INC.
To: HERCULES CAPITAL, INC., AS AGENT
Reel/Frame 058533/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2020
From: DEO, SATISH D
To: FUNGIBLE, INC.
Reel/Frame 052141/0043 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2019
From: HOU, YVONNE; MEKAD, SUNIL; SIRISHE, PRATHAP; BADUSHA, UMAR
To: FUNGIBLE, INC.
Reel/Frame 050220/0225 →
Priority Claims (1)
IN 201841032795 · Aug 31, 2018 · national
Continuity (1)
Related Publication 20200074083A1 · Mar 5, 2020