IP Library Granted Patent US 11,264,215
Granted Patent B2
US 11,264,215 · App. 16/557,257 · Granted Mar 1, 2022

Semiconductor manufacturing apparatus

Inventors: Toshiaki Asai (Nagoya Aichi, JP); Noriyuki Asami (Yokkaichi Mie, JP)
Assignee: Kioxia Corporation
H01J37/32642C23C16/4585C23C16/50H01J37/32715H01L21/68785H01J2237/3321
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Quick Facts
Patent No.
US 11,264,215
App. No.
16/557,257
Granted
Mar 1, 2022
Kind
B2
Abstract

A semiconductor manufacturing apparatus includes: a stage configured to support a semiconductor substrate; and a conductive annular member provided at an outer circumferential portion of the stage and configured to enclose the semiconductor substrate when supported on the stage. The stage has a groove that is provided below a lower portion of an inner circumferential end of the annular member.

Claims (14)

1. A semiconductor manufacturing apparatus comprising:

a stage configured to support a semiconductor substrate; and

a conductive annular member provided at an outer circumferential portion of the stage and configured to enclose the semiconductor substrate when supported on the stage,

wherein the stage has a groove that is provided below a lower portion of an inner circumferential end of the annular member, with a portion of the groove directly exposed by the inner circumferential end;

wherein the groove has an inner edge portion and an outer edge portion, with the lower portion of the inner circumferential end interposed therebetween.

2. The semiconductor manufacturing apparatus according to claim 1 , wherein the groove is an annular groove that is provided along the circumference of the inner circumferential end of the annular member.

3. The semiconductor manufacturing apparatus according to claim 2 , wherein the groove has an inner edge portion that is located on a center side of the stage from the lower portion of the inner circumferential end, and the groove has an outer edge portion that is located on an outer circumferential side of the stage from the lower portion of the inner circumferential end.

4. The semiconductor manufacturing apparatus according to claim 3 , wherein the stage has a mounting area configured to mount the semiconductor substrate, and the inner edge portion of the groove is located below the mounting area.

5. The semiconductor manufacturing apparatus according to claim 1 , wherein the groove has an inner edge portion that is located on a center side of the stage from the lower portion of the inner circumferential end, and the groove has an outer edge portion that is located on an outer circumferential side of the stage from the lower portion of the inner circumferential end.

6. The semiconductor manufacturing apparatus according to claim 1 , wherein the groove comprises a first inner groove and a second outer groove.

7. The semiconductor manufacturing apparatus according to claim 6 , wherein the conductive annular member extends over the second outer groove.

8. The semiconductor manufacturing apparatus according to claim 7 , wherein the conductive annular member does not extend over the first inner groove.

9. The semiconductor manufacturing apparatus according to claim 1 , wherein the groove comprises a plurality of portions that are separated from each other.

10. The semiconductor manufacturing apparatus according to claim 1 , wherein the inner circumferential end of the annular member is a slanted surface.

Assignments (2)
CHANGE OF NAME Recorded Jan 17, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058751/0379 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2020
From: ASAI, TOSHIAKI; ASAMI, NORIYUKI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051702/0847 →
Priority Claims (1)
JP JP2019-033178 · Feb 26, 2019 · national
Continuity (1)
Related Publication 20200273679A1 · Aug 27, 2020