IP Library Granted Patent US 11,257,751
Granted Patent B2
US 11,257,751 · App. 16/557,351 · Granted Feb 22, 2022

Semiconductor device with step-like wiring layers and manufacturing method thereof

Inventor: Yoshinori Ito (Yokkaichi Mie, JP)
Assignee: Toshiba Memory Corporation
H01L23/5226H01L21/76802H01L21/76831H01L21/76877H01L23/5283
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Quick Facts
Patent No.
US 11,257,751
App. No.
16/557,351
Granted
Feb 22, 2022
Kind
B2
Abstract

A device includes: a substrate; a first wiring layer above the substrate; a second wiring layer above the first wiring layer; a first insulating film on the first and second wiring layers; a second insulating film in the first insulating film, provided at a position overlapping with a part of the first wiring layer and a part of the second wiring layer in a first direction perpendicular to a surface of the substrate, and including a first portion higher than an upper surface of an end portion of the second wiring layer and a second portion lower than the upper surface of the end portion of the second wiring layer; and a plug via the second insulating film in the first insulating film, provided on the upper surface of the end portion of the second wiring layer, and electrically connected to the second wiring layer.

Claims (26)

1. A semiconductor device comprising:

a substrate;

a first wiring layer, provided above the substrate, that extends along a first direction;

a second wiring layer, provided above the first wiring layer, that extends along the first direction, wherein the first wiring layer includes an extended portion extending beyond an end portion of the second wiring layer along the first direction;

a first insulating film provided on the first and second wiring layers;

a second insulating film extending into the first insulating film; and

a plug, extending into the first insulating film, that is electrically connected to the second wiring layer,

wherein the second insulating film includes: a first portion above an upper surface of the end portion of the second wiring layer; and a second portion below the upper surface, and wherein the plug is surrounded by and in contact with the first portion.

2. The semiconductor device according to claim 1 , wherein the plug is electrically connected to the second wiring layer via at least the upper surface of the end portion and is electrically insulated from the first wiring layer via at least the second portion of the second insulating film.

3. The semiconductor device according to claim 1 , wherein the second portion is provided along a side surface of the end portion of the second wiring layer.

4. The semiconductor device according to claim 1 , wherein the second portion is in contact with an upper surface of the first wiring layer.

5. The semiconductor device according to claim 1 , wherein the second portion is provided at the extended portion of the first wiring layer.

6. The semiconductor device according to claim 1 , wherein a film thickness of the second insulating film is ½ or more of a width of the second portion at a height of the upper surface of the end portion of the second wiring layer.

7. A method of manufacturing a semiconductor device, the method comprising:

forming, above a substrate, a first wiring layer extending along a first direction;

forming, above the first wiring layer, a second wiring layer extending along the first direction, wherein the first wiring layer includes an extended portion extending beyond an end portion of the second wiring layer along the first direction;

forming a first insulating film on the first and second wiring layers;

forming a hole in the first insulating film, the hole including a first region formed above an upper surface of the end portion of the second wiring layer, and a second region formed below the upper surface of the end portion of the second wiring layer;

forming a second insulating film in the hole, the second insulating film including a first portion formed in the first region and a second portion formed in the second region; and

forming a plug in the hole, the plug formed on the upper surface of the end portion of the second wiring layer to be electrically connected to the second wiring layer;

wherein the plug is surrounded by and in contact with the first portion, the first region is covered with the second insulating film, and the second region is embedded with the second insulating film.

8. The method according to claim 7 , wherein forming a hole further comprises:

exposing, by the first region of the hole, at least one side surface of the first insulating film, and, by the second region of the hole, at least a side surface of the end portion of the second wiring layer.

9. The method according to claim 7 , wherein the second insulating film is a conformal layer in the hole.

10. The method according to claim 7 , wherein the plug is electrically insulated from the first wiring layer via at least the second portion of the second insulating film.

11. The method according to claim 7 , wherein a film thickness of the second insulating film is ½ or more of a width of the second portion at a height of the upper surface of the end portion of the second wiring layer.

Assignments (2)
CHANGE OF NAME Recorded Jan 17, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058751/0379 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2020
From: ITO, YOSHINORI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051703/0006 →
Priority Claims (1)
JP JP2019-048648 · Mar 15, 2019 · national
Continuity (1)
Related Publication 20200294913A1 · Sep 17, 2020