Semiconductor storage device

1. A semiconductor storage device, comprising:

a first memory string unit including a first memory string, the first memory string having a first string selection transistor at a first end and a second string selection transistor at a second end, a plurality of memory cell transistors being connected in series between the first and second string selection transistors;

a bit line connected to an end of the first string selection transistor;

a source line connected to an end of the second string selection transistor;

a word line connected to a gate of a memory cell transistor in the plurality of memory cell transistors;

a first selection line connected to a gate of the first string selection transistor;

a second selection line connected to a gate of the second string selection transistor;

a block selection circuit including a plurality of block selection transistors respectively connected to the first selection line, the word line, and the second selection line,

an equalizer circuit including a first connection transistor having a first end connected to the first selection line via the block selection circuit and a second end connected to the source line, a second connection transistor having a first end connected to the word line via the block selection circuit and a second end connected to the source line, and a third connection transistor having a first end connected to the second selection line via the block selection circuit and a second end connected to the source line; and

a sequencer configured to switch the first, second, and third connection transistors from a non-conductive state to a conductive state after an erase voltage has been applied to the source line during an erasing operation.

2. The semiconductor storage device according to claim 1 , further comprising:

a source line driver connected to the source line and configured to supply voltages to source line; and

a fourth connection transistor connected between the equalizer circuit and the source line driver, the fourth connection transistor being between the source line driver and the source line and configured to electrically connect and disconnect the source line driver from the source line.

3. The semiconductor storage device according to claim 2 , further comprising:

a plurality of memory cell array areas, each including a plurality of memory blocks including a plurality of memory strings, wherein

the source line driver and the equalizer circuit are between adjacent memory cell array areas of the plurality of memory cell array areas, and

one of the adjacent memory cell array areas includes a memory block including the first and second memory strings.

4. The semiconductor storage device according to claim 2 , wherein gates of the first, second, and third connection transistors are connected to each other in common.

5. The semiconductor storage device according to claim 1 , wherein gates of the first, second, and third connection transistors are connected to each other in common.

6. The semiconductor storage device according to claim 1 , wherein the equalizer circuit further includes:

a fourth connection transistor connected between the second end of the first connection transistor and the source line;

a fifth connection transistor connected between the second end of the second connection transistor and the source line; and

a sixth connection transistor connected between the second end of the third connection transistor and the source line.

7. The semiconductor storage device according to claim 6 , wherein the first, second, and third connection transistors are a first type of field effect transistor and the fourth, fifth, and sixth connection transistors are a second type of field effect transistor different from the first type.

8. The semiconductor storage device according to claim 1 , wherein the plurality of memory cell transistors includes at least one dummy memory cell transistor.