Verification apparatus and method for verifying operation of integrated circuit

1. A method for verifying a logic operation of a target circuit including a circuit module configured to dynamically switch between synchronous transfer and asynchronous transfer of a data signal from a transmission side operable in accordance with a first clock signal to a reception side operable in accordance with a second clock signal that is synchronous or asynchronous with the first clock signal, the method comprising:

setting a time window for detecting an erroneous change of a logical value of the data signal based on circuit data of the target circuit, wherein the time window ranges a first time period forward from an edge of the first clock signal and a second time period backward from the edge and excludes a sub range ranging a third time period forward from the edge and a fourth time period backward from the edge, the third time period shorter than the first time period, and the fourth time period shorter than the second time period;

starting a simulation of operation of the target circuit using the circuit data;

during the simulation, determining whether or not the erroneous change of the logical value of the data signal is detected during the set time window;

upon determining that the erroneous change is detected during the set time window, inserting, into a test vector for the simulation, an erroneous sample that causes the reception side to fail in correctly receiving the data signal; and

upon determining that the erroneous change is not detected during the set time window, continuing the simulation without inserting the erroneous sample into the test vector.

2. The method according to claim 1 , further comprising:

during the simulation, determining whether or not the erroneous change of the logical value of the data signal is detected during the sub range; and

upon determining that the erroneous change is detected during the sub range, continuing the simulation without inserting the erroneous sample into the test vector.

3. The method according to claim 1 , further comprising:

during the simulation, determining whether or not a synchronous transfer condition that the circuit module performs the synchronous transfer from the transmission side to the reception side is satisfied; and

upon determining that the synchronous transfer condition is satisfied, continuing the simulation without inserting the erroneous sample into the test vector.

4. The method according to claim 3 , further comprising:

obtaining the synchronous transfer condition from the circuit data.

5. The method according to claim 4 , further comprising:

performing an operation to detect the circuit module in the target circuit based on the circuit data; and

upon the circuit module being detected, performing an operation to detect the synchronous transfer condition from the circuit data.

6. The method according to claim 5 , further comprising:

upon the synchronous transfer condition being detected, storing the synchronous transfer condition in association with the circuit module in a database; and

during the simulation, whether or not the synchronous transfer condition is satisfied is determined based on the synchronous transfer condition stored in the database.

7. The method according to claim 1 , wherein lengths of the third and fourth time periods are set such that the erroneous change of the logical value of the data signal does not occur during the third and fourth time periods when the circuit module performs the synchronous transfer from the transmission side to the reception side.

8. The method according to claim 1 , further comprising:

setting a clock skew of the first clock signal and the second clock signal, such that the erroneous change of the logical value of the data signal does not occur during the third and fourth time periods when the circuit module performs the synchronous transfer from the transmission side to the reception side.

9. The method according to claim 1 , wherein the edge of the first clock signal is a rising edge.

10. The method according to claim 1 , wherein the second time period is a set up time period of the first clock signal, and the first time period is a hold time period of the first clock signal.

11. A verification apparatus for verifying a logic operation of a target circuit including a circuit module configured to dynamically switch between synchronous transfer and asynchronous transfer of a data signal from a transmission side operable in accordance with a first clock signal to a reception side operable in accordance with a second clock signal that is synchronous or asynchronous with the first clock signal, the apparatus comprising a processor configured to:

set a time window for detecting an erroneous change of a logical value of the data signal based on circuit data of the target circuit, wherein the time window ranges a first time period forward from an edge of the first clock signal and a second time period backward from the edge and excludes a sub range ranging a third time period forward from the edge and a fourth time period backward from the edge, the third time period shorter than the first time period, and the fourth time period shorter than the second time period;

start a simulation of operation of the target circuit using the circuit data;

during the simulation, determine whether or not the erroneous change of the logical value of the data signal is detected during the set time window;

upon determining that the erroneous change is detected during the set time window, insert, into a test vector for the simulation, an erroneous sample that causes the reception side to fail in correctly receiving the data signal; and

upon determining that the erroneous change is not detected during the set time window, continue the simulation without inserting the erroneous sample into the test vector.

12. The verification apparatus according to claim 11 , wherein the processor is further configured to:

during the simulation, determine whether or not the erroneous change of the logical value of the data signal is detected during the sub range; and

upon determining that the erroneous change is detected during the sub range, continue the simulation without inserting the erroneous sample into the test vector.

13. The verification apparatus according to claim 11 , wherein the processor is further configured to:

during the simulation, determine whether or not a synchronous transfer condition that the circuit module performs the synchronous transfer from the transmission side to the reception side is satisfied; and

upon determining that the synchronous transfer condition is satisfied, continue the simulation without inserting the erroneous sample into the test vector.

14. The verification apparatus according to claim 13 , wherein the processor is further configured to obtain the synchronous transfer condition from the circuit data.

15. The verification apparatus according to claim 14 , wherein the processor is further configured to:

perform an operation to detect the circuit module in the target circuit based on the circuit data; and

upon the circuit module being detected, perform an operation to detect the synchronous transfer condition from the circuit data.

16. The verification apparatus according to claim 15 , wherein the processor is further configured to:

upon the synchronous transfer condition being detected, store the synchronous transfer condition in association with the circuit module in a storage device; and

during the simulation, determine whether or not the synchronous transfer condition is satisfied based on the synchronous transfer condition stored in the storage device.

17. The verification apparatus according to claim 11 , wherein the processor is further configured to set lengths of the third and fourth time periods such that the erroneous change of the logical value of the data signal does not occur during the third and fourth time periods when the circuit module performs the synchronous transfer from the transmission side to the reception side.

18. The verification apparatus according to claim 11 , wherein the processor is further configured to set a clock skew of the first clock signal and the second clock signal, such that the erroneous change of the logical value of the data signal does not occur during the third and fourth time periods when the circuit module performs the synchronous transfer from the transmission side to the reception side.

19. The verification apparatus according to claim 11 , wherein the edge of the first clock signal is a rising edge.

20. The verification apparatus according to claim 11 , wherein the second time period is a set up time period of the first clock signal, and the first time period is a hold time period of the first clock signal.